FORM 160.54-O1
ISSUE DATE: 9/10/2014
JOHNSON CONTROLS
72
SECTION 2 - OPTIVIEW CONTROL CENTER INTRODUCTION
ACC Surge Detected (LED)
(Software version C.OPT.01.23.307 and later)
Only displayed if equipped with a VSD (in Modbus
Protocol Configuration) or MV VSD. Illuminates mo-
mentarily when a surge is detected by the ACC func-
tion in the Microboard, while the drive is running at
less than maximum frequency.
VGD Count
Displays the number of times the Stall Detector Board
output voltage goes above the High Limit Setpoint.
The count can be reset with an ADMIN access level
using the VGD CYCLE COUNT key on the VGD
SETPOINTS Screen.
VGD Time ( __Days __Hrs __Min __Sec)
Displays the accumulated time the Stall Detector Board
output voltage is greater than the High Limit Setpoint
while the chiller is running.
Control Status
Displays the current state of the VGD control. The
states are: Stall Waiting, Stall Reacting, Probing, Surge
Reacting, Surge Waiting, Hot Gas Override.
Time Remaining
While the VGD is in the Stall Waiting State, displays
the time remaining in the Probe Wait Time interval
(value programmed as the Probe Wait Time setpoint).
PROGRAMMABLE
Surge React
(1 to 30 seconds; default 5) – Specifies the length of the
close pulse applied to the VGD in response to a surge.
PRV Offset
(0 to 5%; default 3) – If the VGD control is in the
Stall Waiting state and the Pre-rotation Vanes position
changes by more than this value, the Probing state will
be entered. If the PRV Offset is set to 0%, the Stall
Waiting state is performed based only on the Probe
Wait Time setpoint interval.
Probe Wait
(0.5 to 15 minutes; default 10) – Specifies how long
the VGD control remains in the Stall Waiting or Surge
Waiting states before entering the Probing state.
Open Pulse
(1 to 9 seconds; default 2) – Specifies the length of the
open pulse applied to the VGD during 10 second peri-
ods while in the Probing state.
High Limit
(0.5 to 1.2VDC; default 0.6VDC; (0.8VDC with soft-
ware version C.OPT.01.22.307 or earlier) – Specifies
the Stall Detector Board output voltage that represents
an acceptable amount of stall noise.
The minimum difference between the High Limit
Setpoint and the Low Limit Setpoint is 0.1VDC. If
a Low Limit Setpoint is entered which is less than
0.1VDC below the High Limit Setpoint, the High Lim-
it Setpoint is adjusted so that it is 0.1VDC above the
newly entered Low Limit value.
Low Limit
(0.4 to 0.8VDC; default 0.5VDC; (0.6VDC with soft-
ware version C.OPT.01.22.307 or earlier) – in the Stall
Reacting State, the VGD is driven closed until the Stall
Detector Board output voltage decreases to this level.
The minimum difference between the High Limit
Setpoint and the Low Limit Setpoint is 0.1VDC. If
a Low Limit Setpoint is entered which is less than
0.1VDC below the High Limit Setpoint, the High Lim-
it Setpoint is adjusted so that it is 0.1VDC above the
newly entered Low Limit value.
VGD Count
Access Level Required: ADMIN
Allows the user to clear the VGD Cycle Count.
Extreme Stall Duration
(Software version C.MLM.01.14.xxx (and later) or
C.OPT.01.14.306 (and later))
(10 to 20 minutes; default 10) – Specifies the maxi-
mum allowed time an extreme stall condition can exist
before the VGD operation is disabled and driven to the
full open position to protect it from damage.
PRV VGD Inhibit
(Software version C.OPT.01.14.xxx and later)
[40% - 100% default 100% (95% with software version
C.OPT.01.22.307 and earlier)] While the Pre-rotation
Vanes position is greater than this setpoint, extreme
stall conditions are not checked, the VGD control is
inhibited and the VGD is pulsed open according to the
Open Pulse Setpoint. While this is in effect, PRV Posi-
tion Override is displayed as Control Status.
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