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Status Registers
Status Register System
The status byte register contains the following bits:
To query the status byte register, send the *STB command.
The response will be the decimal sum of the bits that are
set to 1. For example, if bit number 7 and bit number 3 are
set to 1, the decimal sum of the 2 bits is 128 plus 8. So the
decimal value 136 is returned.
Bit Description
0,1 Unused: These bits are always set to 0.
2 Error/Event Queue Summary Bit: A 1 in this bit position
indicates that the SCPI error queue is not empty. The SCPI error
queue contains at least one error message.
3 Questionable Status Summary Bit: A 1 in this bit position
indicates that the questionable status summary bit has been set.
The questionable status event register can then be read to
determine the specific condition that caused this bit to be set.
4 Message Available (MAV): A 1 in this bit position indicates
that the analyzer has data ready in the output queue. There are
no lower status groups that provide input to this bit.
5 Standard Event Status Summary Bit: A 1 in this bit position
indicates that the standard event status summary bit has been set.
The standard event status register can then be read to determine
the specific event that caused this bit to be set.
6
Request Service (RQS) Summery Bit: A 1 in this bit position
indicates that the analyzer has at least one reason to report a sta-
tus change. This bit is also called the master summary status bit
(MSS).
7
Operation Status Summary Bit: A 1 in this bit position indi-
cates that the operation status summary bit has been set. The
operation status event register can then be read to determine the
specific event that caused this bit to be set.
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