signal:
①. The GND channel of the logic analyzer is connected to the GND of the test system, and 2
signal channels are connected to RXD and TXD pins of the level shift chip respectively.
②. The GND channel of the logic analyzer is connected to the L end of CAN bus, and 1 signal
channel is connected to the H end of CAN bus.
③. Connect the CAN bus to a module that transfer CAN to TTL, and the GND and a signal
channel of the logic analyzer are connected to the GND and signal export end of the system under
test.
Most of the time, all these 3 ways could be used to sample the signal, but according to CAN
specification, the voltage between the H-L ends is 0V and 2V. In complicated situations, such as
master with many slaves or long wire, the difference of the bus end could be too little, and the logic
analyzer could not identify the signal level correctly with method 2. In addition, the GND channel
of method 2 need to be connected to the CAN-L end, but if other signals need to be tested at the
same time, the grounding could be confusing. So method 1 and method 3 are recommended if
conditions permit.
5、 Simple Parallel
The setting dialog of simple parallel analyzer is shown below:
1-8 items, the channels used for 8 parallel ports.
9
th
item. the channel used for clock signal of data latch.
10
th
item, data latch on the rising edge(Data is valid on Clock rising edge) of clock signal or
falling edge(Data is valid on Clock falling edge).
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