passing a value of 0 corresponds to a factor of 256, and thus a maximum frequency of
he initial state of SCK is set properly (CPOL), by this function, before CS (chip select) is
se (CPHA) is 1, data is valid on the edge going to CPOL. If CPHA is 0, data is valid
on the edge going away from CPOL. Clock Polarity (CPOL) determines the idle state of SCK.
Up to 50 bytes can be written/read. Communication is full duplex so 1 byte is read at the same
time each byte is written.
about 125 kHz.
• CS/CLK/MISO/MOSI -PinNum: Assigns which digital I/O line is used for each SPI line.
Value passed is 0-19 corresponding to the normal digital I/O numbers as specified in
Section 2.8.
• NumSPIBytesToTransfer: Specifies how many SPI bytes will be transferred (1-50).
T
brought low (final state is also set properly before CS is brought high again). If CS is being
handled manually, outside of this function, care must be taken to make sure SCK is initially set
to CPOL before asserting CS.
All standard SPI modes supported (A, B, C, and D).
Mode A: CPHA=1, CPOL=1
Mode B: CPHA=1, CPOL=0
Mode C: CPHA=0, CPOL=1
Mode D: CPHA=0, CPOL=0
If Clock Pha
107
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