2.9.1.10 System Timer Low/High Read (Modes 10 & 11)
The LabJack U3 has a free-running internal 64-bit system timer with a frequency of 4 Mz. Timer
modes 10 & 11 return the lower or upper 32-bits of this timer. An FIO line is allocated for these
modes like normal, even though they are internal readings and do not require any external
connections. This system timer cannot be reset, and is not affected by the timer clock.
If using both modes 10 & 11, read both in the same low-level command and read 10 before 11.
2.9.1.11 Period Measurement (16-Bit, Modes 12 & 13)
Similar to the 32-bit edge-to-edge timing modes described above (modes 2 & 3), except that
hardware capture registers are used to record the edge times. This limits the times to 16-bit
values, but is accurate to the resolution of the clock, and not subject to any errors due to
firmware processing delays.
Note that the minimum measurable period is limited by the edge rate limit discussed in Section
2.9.2.
2.9.2 Timer Operation/Performance Notes
Note that the specified timer clock frequency is the same for all timers. That is, TimerClockBase
and TimerClockDivisor are singular values that apply to all timers. Modes 0, 1, 2, 3, 4, 7, 12,
and 13, all are affected by the clock frequency, and thus the simultaneous use of these modes
has limited flexibility. This is often not an issue for modes 2 and 3 since they use 32-bit
registers.
The output timer modes (0, 1, and 7) are handled totally by hardware. Once started, no
processing resources are used and other U3 operations do not affect the output.
The edge-detecting timer input modes do require U3 processing resources, as an interrupt is
required to handle each edge. Timer modes 2, 3, 5, 9, 12, and 13 must process every
applicable edge (rising or falling). Timer modes 4 and 8 must process every edge (rising and
falling). To avoid missing counts, keep the total number of processed edges (all timers) less
than 30,000 per second (hardware V1.21). That means that in the case of a single timer, there
should be no more than 1 edge per 33 μs. For multiple timers, all can process an edge
simultaneously, but if for instance both timers get an edge at the same time, 66 μs should be
allowed before any further edges are applied. If streaming is occurring at the same time, the
maximum edge rate will be less (7,000 per second), and since each edge requires processing
time the sustainable stream rates can also be reduced.
2.10 SCL and SDA (or SCA)
Reserved for future use.
2.11 DB15
The DB15 connector brings out 12 additional digital I/O. It has the potential to be used as an
expansion bus, where the 8 EIO are data lines and the 4 CIO are control lines.
In the Windows LabJackUD driver, the EIO are addressed as digital I/O bits 8 through 15, and
the CIO are addressed as bits 16-19.
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