960L Multi-Channel Digital Effects System Service Manual
7-42
Read burst 4 0
4
Generated by read buffer or DMA request.
Read burst 8 0 Generated by cache line fills or read buffer
requests.
Write single 1 Any 1..4 bytes are written as specified by byte mask.
Generated by write buffer or DMA request.
Write burst 2 0, 1, 2,
4, 5, 6
All four bytes of each word are written.
Generated by write buffer or DMA request.
Write burst 3 0, 1
4, 5
All four bytes of each word are written.
Generated by write buffer or DMA request.
Write burst 4 0
4
All four bytes of each word are written.
Generated by write buffer or DMA request.
Write burst 8 0 Cache line copyback. All 32 bytes are written.
Table 3-1 SA-1100 Transactions
Refresh timing
The SA-1100 provides support for a CAS before RAS (CBR) refresh cycle which is shown below.
CPU CLOCK
MEM CLOCK
SA_RAS
SA_CAS
Figure 3-1 Refresh Timing
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