Lexicon 960L - Page 121

Lexicon
7-43
Read-Write timing
CPU CLK
MEM CLK
SA_ADDR
SA_RAS
SA_CAS
Mem DQ
ROW + BANK
SA_OE
Reads:
Writes:
Mem DQ
SA_WE
WR DATA
RD DATA
MDCAS0 = 1100 0001 1111 0000 0111 1100 0001 1111
MDCAS1 = 1111 0000 0111 1100 0001 1111 0000 0111
MDCAS2 = 1111 1111 1111 1111 0000 0111 1100 0001
MDCNFG:TRP=4 MDCNFG:CDB2 = 0 TDL=00
Figure 3-2 Dram Single Transactions
MEM CLK
Last <------------------------------------------------------
-
MDCAS1=1100 MDCAS0=1100 1100 1100 1100 1100 1100 1100 0111
MDCNFG:TRP=4 MDCNFG:CDB2 = 0 TDL=00
SA_ADDR
SA_RAS
SA_CAS
Mem DQ
ROW+BANK
SA_OE
Reads:
Writes:
Mem DQ
SA_WE
COL
COL+4 COL+8 COL+12
RD0 RD1
RD2
RD3
WD0 WD1 WD2 WD3
Figure 3-3 Dram Burst Transactions
Boot Flash (U12, sheet 2)
The Boot Flash is a 1 Mbit 3 Volt Flash memory organized as 64 k words by 16 bits. The chip is mounted in
a 44-pin PLCC socket. The Boot Flash is programmed prior to insertion onto the board but there is code in
the Boot Flash to perform updates to the code. The memory is not byte-writeable and must be programmed
on a half word boundary (16 bits).