Lexicon 960L - Page 129

Lexicon
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1000 0702 PS/2STAT PS/2 Status Register
1800 0000 – 1800 0002 CS3REG CS3 Register
2000 0000 – 2000 FFFF PCMCIA socket 1 I/O space
2800 0000 – 2800 FFFF PCMCIA socket 1 attribute space
2C00 0000 – 2C00 FFFF PCMCIA socket 1 memory space
3000 0000 – 3000 FFFF PCMCIA socket 2 I/O space
3800 0000 – 3800 FFFF PCMCIA socket 2 attribute space
3C00 0000 – 3C00 FFFF PCMCIA socket 2 Memory space
8000 0000 UDCCR UDC control register
8000 0004 UDCAR UDC address register
8000 0008 UDCOMP UDC OUT max packet register
8000 000C UDCIMP UDC IN max packet register
8000 0010 UDCCS0 UDC endpoint 0 cntl/status reg
8000 0014 UDCCS1 UDC endpoint 1 cntl/status register
8000 0018 UDCCS2 UDC endpoint2 cntl/status register
8000 001C UDCD0 UDC endpoint 0 data register
8000 0020 UDCWC UDC endpoint 0 write count register
8000 0028 UDCDR UDC xmit/rec data register (fifo)
8001 0000 UT1CR0 UART 1 control register 0
8001 0004 UT1CR1 UART 1 control register 1
8001 0008 UT1CR2 UART 1 control register 2
8001 000C UT1CR3 UART 1 control register 3
8001 0014 UT1DR UART 1 data register
8001 001C UT1SR0 UART 1 status register 0
8001 0020 UT1SR1 UART 1 status register 1
8002 0060 SDCR0 SDLC control register 0
8002 0064 SDCR1 SDLC control register 1
8002 0068 SDCR2 SDLC control register 2
8002 006C SDCR3 SDLC control register 3
8002 0070 SDCR4 SDLC control register 4
8002 0078 SDDR SDLC data register
8002 0080 SDSR0 SDLC status register 0
8002 0084 SDSR1 SDLC status register 1
8003 0000 UT2CR0 UART 2 control register 0
8003 0004 UT2CR1 UART 2 control register 1
8003 0008 UT2CR2 UART 2 control register 2
8003 000C UT2CR3 UART 2 control register 3
8003 0010 UT2CR4 UART 2 control register 4
8003 0014 UT2DR UART 2 data register
8003 001C UT2SR0 UART 2 status register 0
8003 0020 UT2SR1 UART 2 status register 1
8004 0060 HSCR0 HSSP control register 0
8004 0064 HSCR1 HSSP control register 1