Lexicon 960L - Page 130

960L Multi-Channel Digital Effects System Service Manual
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8004 006C HSDR HSSP data register
8004 0070 HSSR0 HSSP status register 0
8004 0078 HSSR1 HSSP status register 1
8005 0000 UT3CR0 UART 3 control register 0
8005 0004 UT3CR1 UART 3 control register 1
8005 0008 UT3CR2 UART 3 control register 2
8005 000C UT3CR3 UART 3 control register 3
8005 0014 UT3DR UART 3 data register
8005 001C UT3SR0 UART 3 status register 0
8005 0020 UT3SR1 UART 3 status register 1
8006 0000 MCCR0 MCP control register 0
8006 0008 MCDR0 MCP data register 0
8006 000C MCDR1 MCP data register 1
8006 0018 MCSR MCP Status register
8007 0060 SSCR0 SSP control register 0
8007 0064 SSCR1 SSP control register 1
8007 006C SSDR SSP data register
8007 0074 SSSR SSP status register
9000 0000 OSMR0 OS timer match register 0
9000 0004 OSMR1 OS timer match register 1
9000 0008 OSMR2 OS timer match register 2
9000 000C OSMR3 OS timer match register 3
9000 0010 OSCR OS timer counter register
9000 0014 OSSR OS timer status register
9000 0018 OWER OS timer watchdog enable register
9000 001C OIER OS timer interrupt enable register
9001 0000 RTCAR Real-time clock alarm register
9001 0004 RTCNR Real-time clock count register
9001 0008 RTCTR Real-time clock trim register
9001 0010 RTCSR Real-time clock status register
9002 0000 PMCR Power manager control register
9002 0004 PSSR Power manager sleep status register
9002 0008 PSPR Power manager scratchpad register
9002 000C PWER Power manager wakeup enable register
9002 0010 PCFR Power manager configuration register
9002 0014 PPCR Power manager PLL configuration
9002 0018 PGSR Power manager GPIO sleep state
9002 001C POSR Power manager oscillator status
9003 0000 RSRR Reset controller software reset
9003 0004 RCSR Reset controller status register
9003 0008 TUCR Reserved for test
9004 0000 GPLR GPIO pin level register