P106 Control Board LVDS Connector Voltages and Diode Check
P106 LVDS "Control" to P1401 "Main"
Pin Label Run Diode Check Pin Label Run Diode Check
50 VS_3D *0V OL 25 RE1+ 1.11V 1.31V
49 UART_TXD 3.31V OL 24 RE1- 1.19V 1.31V
48 UART_RXD 3.3V OL 23 RD1+ 1.11V 1.31V
47 n/c n/c OL 22 RD1- 1.19V 1.31V
46 n/c n/c OL 21 Gnd Gnd Gnd
n
n
n
+
.
.
44 Gnd Gnd Gnd 19 RCLK1- 1.13V 1.31V
43 Gnd Gnd Gnd 18 Gnd Gnd Gnd
42 Gnd Gnd Gnd 17 RC1+ 1.11V 1.31V
41 RE3+ 1.11V 1.31V 16 RC1- 1.19V 1.31V
40 RE3- 1.19V 1.31V 15 RB1+ 1.11V 1.31V
39 RD3+ 1.11V 1.31V 14 RB1- 1.19V 1.31V
38 RD3- 1.19V 1.31V 13 RA1+ 1.11V 1.31V
37 Gnd Gnd Gnd 12 RA1- 1.19V 1.31V
36 RCLK3+ 1.16V 1.31V 11 Gnd Gnd Gnd
35 RCLK3- 1.13V 1.31V 10 n/c n/c OL
1
33 RC3+ 1.11V 1.31V 8n/c n/cOL
32 RC3- 1.19V 1.31V 7n/c n/cOL
31 RB3+ 1.11V 1.31V 6 SDA 3.3V OL
30 RB3- 1.19V 1.31V 5 *DISP_EN 3.05V OL
29 RA3+ 1.11V 1.31V 4 SCL 3.3V OL
bit differential video signal
Pin 5 is the reason the LVDS
cable must be removed to use the
EX_AUTO_GEN shorting pins to
create multiple internal generated
test patterns (Panel Test).
Pin 5: Enables the Control Board
28 RA3- 1.19V 1.31V 3 PC_SER_DATA 3.31V OL
27 Gnd Gnd Gnd 2 PC_SER_CLK 3.31V OL
1 Gnd Gnd Gnd
June 2011 42PW350 Plasma
121
Note: There are no voltages in Stand-By mode.