LSIS XGL-EFMT - Device of XGI CPU; Device of XGR CPU

Appendix
A-2
A.1.2 Device of XGI CPU
Device type Size Range Reference
memory
Symbolic variable
area(A)
512K byte
%AW0~%AW262143
Max 256K byte can be set as
retain-area
Input variable(I)
16K byte
%IW0.0.0 ~ %IW127.15.3
-
Output variable(Q) 16K byte
%QW0.0.0 ~ %QW127.15.3
-
Direct
variable
M 256K byte
%MW0~%MW131071
Max 128K byte
can be set as
retain-area
R
64K byte * 2
blocks
%RW0~%RW32767 64K byte per one block
W 128K byte
%WW0~%WW65535
-
Flag
variable
F 4K byte
%FW0~%FW2047
System flag
K 16K byte
%KW0~%KW8399
PID flag
L 22K byte
%LW0~%LW11263
High Speed Link flag
N 42K byte
%NW0~%NW25087
P2P flag
U
8K byte
%UW7.15.31
Analog refresh flag
A.1.3 Device of XGR CPU
Device type
Size
Range
Reference
Memory
Input variable(I) 16KB %IW0.0.0 ~ %IW127.15.3 -
Output variable(Q)
16KB
%QW0.0.0 ~ %QW127.15.3
-
Automatic
variable(A)
512KB
%AW0~%AW262143
Max 256K byte can be set as
retain-area
Direct
variable
M 256KB
%MW0~%MW131071
Max 128K byte can be set as
retain-area
R
64KB * 2
blocks
%RW0~%RW32767 64K byte per one block
W 128KB
%WW0~%WW65535
Same with R area
Flag
variable
F 4KB
%FW0~%FW2047
System flag
K 18KB
%KW0~%KW8399
PID area (PID 256 loop)
L 22KB
%LW0~%LW11263
HS link flag, P2P flag
N 42KB
%NW0~%NW25087
P2P parameter (XG5000
setting)
U 32KB %UW31.15.31
Analog refresh area
( 31 base, 16 slot, 32 channel )