Matrox Solios eV-CL - Page 40

40 Chapter 4: Matrox Solios eV-CL hardware reference
PSG #0
PSG #1
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
SerTFG
SerTC
24
UART
UART
LVDS
drivers
and
receivers
OptoAux (4)
TTL buffers
On a separate bracket.
Aux In (4)
Aux Out (4)
HSYNC Out (2)
VSYNC Out (2)
Clock Out (2)
Optocoupler
Aux I/Os (6)
ChannelLink
Receiver #2
Clock
Data (24)
& Syncs (4)*
24
LUTs
LUTs
32
32
Cam Ctrl (4)
Cam Ctrl (4)
LVDS
drivers
LVDS
drivers
LVDS driver
& receiver
LVDS driver
& receiver
Demultiplexer
Demultiplexer
Acquisition section of
Matrox Solios eV-CLBL
dual-Base configuration
28 bits serialized across 4 LVDS pairs.*
**
Camera Link
connector 0
(MDR-26)
Camera Link
connector 1
(MDR-26)
External Auxiliary
I/O connectors
()
**
DBHD-44 and DB-9
Video to
PCI-X
Bridge