Matrox Solios eV-CL - Page 43

Matrox Solios eV-CL acquisition section 43
PSG #0
Camera Link
Connector 0
(mini HDR-26)
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
Camera Link
connector 1
(mini HDR-26)
24
UART
LVDS
transceivers
OptoAux (2)
External Auxiliary
I/O connector 0
(DBHD-15)
TTL buffers
Aux In (2)
Aux Out (1)
Optocoupler
Aux I/Os (3)
External Auxiliary
I/O connector 1
(DBHD-15 or DB-9)**
LVDS
transceivers
OptoAux (2)
TTL buffers
Aux In (2)
Optocoupler
Aux I/Os (1)
Cam Ctrl (4)
LVDS
drivers
LVDS driver
& receiver
LUTs
64
ChannelLink
Receiver #2
Clock
Data (28)*
28
ChannelLink
Receiver #3
Clock
Data (28)*
28
Demultiplexer
On a separate bracket. Note that on a DB-9 connector, not all depicted
signals are used.
28 bits serialized across 4 LVDS pairs. In single-Medium mode,
ChannelLink Receiver #2 can only receive 24 bits of data and
ChannelLink Receiver #3 is not used.
*
**
Video to
PCI-X
Bridge
Acquisition section of
Matrox Solios eV-CLF