Matrox Solios eV-CL - Page 55

Matrox Solios eV-CL acquisition section 55
Type of signal
A
c
q
u
i
s
i
t
i
o
n
p
a
t
h
LV DS cam. ctrl Received with data
LVD S dedicated signals
*
CL connect. 0 CL connect. 1
C
L
c
o
n
n
e
c
t
.
0
C
L
c
o
n
n
e
c
t
.
1
C
C
1
C
C
2
C
C
3
C
C
4
C
C
1
C
C
2
C
C
3
C
C
4
Frame valid input 00
10
VSYNC output 00000 P0_LVDS_VSYNC_OUT
1 0000 P1_LVDS_VSYNC_OUT
Line valid input 00
10
HSYNC output 00000 P0_LVDS_HSYNC_OUT
1 0000 P1_LVDS_HSYNC_OUT
Data valid input 00
10
Clock input 0 Xclk (CL connect. 0)
1 Xclk (CL connect. 1)
Clock output 00000 P0_LVDS_CLK_OUT
1 0000 P1_LVDS_CLK_OUT
*. In this column, each signal is a dedicated signal (that is, it cannot be redefined as another type of signal). In addition, clock input is received on the Camera
Link connectors, whereas the other signals in this column are received on/transmitted from external auxiliary I/O connector 0 (DBHD-44).