Serial Interface
A serial interface is used to program the MAX2771 for
configuring the different operating modes. The serial
interface is controlled by three signals: SCLK (serial clock),
CSN (chip select), and SDATA (serial data). The interface
is based on the industry-standard Serial Peripheral
Interface (SPI). The MAX2771 is a SPI slave and the
device responsible for programming the MAX2771, such
as a microprocessor or baseband controller, is the SPI
master. The SPI master will be referred to henceforth as
the “host”. The host is responsible for driving SCLK, CSN,
and SDATA. The MAX2771 only drives SDATA at certain
times during the transaction so as to avoid bus contention
with the master.
The transfer of a set of data between host and MAX2771
is referred to as a “SPI transaction”. An SPI transaction
consists of 48 SCLK pulses. The base value of SCLK is
low. Data on SDATA is output on the falling edge of SCLK
and is sampled on the rising edge of SCLK by both host
and the MAX2771.
The SDATA line is normally tri-stated by both the host
and the MAX2771. It can only be driven by the MAX2771
during the latter part of a Read SPI transaction provided
that CSN = 0. SDATA is driven by the host during the
entire SPI transaction in the case of Write transactions,
and only during the first part of Read transactions.
The first 12 bits transferred from host to the MAX2771
during an SPI transaction contain the address of the
register to be accessed. The first 8 bits are always zero,
while the last four bits are the address of the register. The
13th bit transferred from master to MAX2771 is the R/W
bit. If R/W = 1, the transaction is a read and the MAX2771
will drive SDATA in the latter part of the transaction. If R/W
= 0, the transaction is a write, and the host will continue
to drive SDATA for the remainder of the transaction. The
14th through 16th bits are turnaround bits that are denoted
T
A
. The purpose of these bits is to allow time for the bus
to change direction in the case of a read and so avoid
any possible contention for the bus. In the case of a read
transaction, the host releases SDATA during this interval,
and the MAX2771 does not yet start driving SDATA. In the
case of a write transaction, the host can continue to drive
SDATA during this interval. The value of the bits is irrelevant
(don’t care). The remaining bits of the transaction are the
data bits. The number of data bits will always be a 32
since all the registers in the MAX2771 are 32-bits wide.
Figure 4 shows a register read transaction. In this
example, a 32 bit register is read by the host. The host
first asserts CSN, begins driving SDATA with the register
address preceded by 8 zeros and starts toggling SCLK.
The MAX2771 samples the bits on SDATA on the rising
edge of SCLK. After the address is output, the host outputs
a R/W bit having value of 1 indicating this a read transac-
tion. The next three bits are the TA bits during which the
host releases the SDATA line. In this figure, SDATA is
shown as tri-stated during this bit interval to emphasize
that nothing is actively driving it. The MAX2771 can be
configured to resistively pull up SDATA, pull it down, or
apply a bus-hold during periods when it is not driving the
bus. The MAX2771 then starts driving SDATA and outputting
the 32 bits of the addressed register starting from the
most significant bit. After the last bit has been output, the
MAX2771 tri-states SDATA, and the host subsequently
brings CSN high completing the transaction.
Table 14. Reference Divider Settings
REFDIV
(PLL CONFIGURATION REGISTER)
CLOCK OUTPUT
000 XTAL frequency x2
001 XTAL frequency ÷4
010 XTAL frequency ÷2
011 XTAL frequency
100 XTAL frequency x4
www.maximintegrated.com
Maxim Integrated
│
25
MAX2771 Multiband Universal GNSS Receiver
To Next Page
Loading...