Maxim Integrated MAX2771 - PLL Configuration (0 X3)

PLL Conguration (0x3)
PLL, VCO and CLK configuration
BIT 31 30 29 28 27 26 25 24
Field REFDIV[2:0] LOBAND RESERVED RESERVED RESERVED REFOUTEN
Reset 0x3 0x0 0x1 0x0 0x0 0x1
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BIT 23 22 21 20 19 18 17 16
Field RESERVED RESERVED[1:0] IXTAL[1:0] RESERVED[4:2]
Reset 0x1 0x0 0x1 0x10
Access Type Write, Read Write, Read Write, Read Write, Read
BIT 15 14 13 12 11 10 9 8
Field RESERVED[1:0] RESERVED RESERVED[2:0] ICP RESERVED
Reset 0x10 0x0 0x0 0x0 0x0
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
BIT 7 6 5 4 3 2 1 0
Field RESERVED RESERVED[2:0] INT_PLL PWRSAV RESERVED RESERVED
Reset 0x0 0x0 0x1 0x0 0x0 0x0
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
REFDIV 31:29 Clock output divider ratio
0x0: XTAL frequency x2
0x1: XTAL frequency /4
0x2: XTAL frequency /2
0x3: XTAL frequency
0x4: XTAL frequency x4
0x5: Reserved
0x6: Reserved
0x7: Reserved
LOBAND 28 Local Oscillator band selection
0x0: L1 band
0x1: L2/L5 band
RESERVED 27 Reserved: DO NOT CHANGE VALUE RESERVED
RESERVED 26 Reserved: DO NOT CHANGE VALUE RESERVED
RESERVED 25 Reserved: DO NOT CHANGE VALUE RESERVED
REFOUTEN 24 Output clock bu󰀨er enable
0x0: Disable clock bu󰀨er
0x1: Enable clock bu󰀨er
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MAX2771 Multiband Universal GNSS Receiver