Maxim Integrated MAX2771 - Clock Configuration 2 (0 Xa)

Clock Conguration 2 (0xA)
Clock Configuration
BIT 31 30 29 28 27 26 25 24
Field RESERVED[2:0] RESERVED ADCCLK_L_CNT[11:8]
Reset 0x0 0x0 256
Access Type Write, Read Write, Read Write, Read
BIT 23 22 21 20 19 18 17 16
Field ADCCLK_L_CNT[7:0]
Reset 256
Access Type Write, Read
BIT 15 14 13 12 11 10 9 8
Field ADCCLK_M_CNT[11:4]
Reset 1563
Access Type Write, Read
BIT 7 6 5 4 3 2 1 0
Field ADCCLK_M_CNT[3:0]
PRE
FRACDIV_
SEL
CLKOUT_
SEL
RESERVED[1:0]
Reset 1563 0x0 0x0 0x0
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RESERVED 31:29 Reserved: DO NOT CHANGE VALUE RESERVED
RESERVED 28 Reserved: DO NOT CHANGE VALUE RESERVED
ADCCLK_
L_CNT
27:16 Sets the value for the L counter
ADCCLK_
M_CNT
15:4 Sets the value for the M counter
PRE
FRACDIV_
SEL
3 Fractional clock divider selection
0x0: Bypass fractional clock divider
0x1: Enable fractional divider
CLKOUT_
SEL
2 CLKOUT selection
0x0: Integer divider/multiplier output
0x1: ADC clock
RESERVED 1:0 Reserved: DO NOT CHANGE VALUE RESERVED
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MAX2771 Multiband Universal GNSS Receiver