Maxim Integrated MAX2771 - Page 36

Conguration 3 (0x2) (continued)
BITFIELD BITS DESCRIPTION DECODE
PGAIEN 13 I-channel PGA enable
0x0: Disable I channel PGA
0x1: Enable I channel PGA
PGAQEN 12 Q-channel PGA enable
0x0: Disable Q channel PGA
0x1: Enable Q channel PGA
STRMEN 11
Enable DSP interface for serial streaming of
data. Congures the IC such that the DSP
interface is inserted in the signal path.
0x0: Disable DSP interface
0x1: Enable DSP interface
STRMSTART 10
The rising edge of this bit enables data
streaming to the output. It also enables clock,
data sync, and frame sync outputs.
STRMSTOP 9
The rising edge of this bit disables data
streaming to the output. It also disables clock,
data sync, and frame sync outputs.
RESERVED 8:6 Reserved: DO NOT CHANGE VALUE RESERVED
STRMBITS 5:4 Number of bits streamed
0x0: Reserved
0x1: I MSB, I LSB
0x2: Reserved
0x3: I MSB, I LSB, Q MSB, Q LSB
STAMPEN 3
Enables the insertion of the frame number at
the beginning of each frame. If disabled, only
the ADC data is streamed to the output.
0x0: Disable frame number insertion
0x1: Enable frame number insertion
TIME
SYNCEN
2
Enables the output of the time sync pulses at
all times when streaming is enabled by the
STRMEN command. Otherwise, the time
sync pulses are available only when data
streaming is active at the output; for example,
in the time intervals bound by the STRM-
START and STRMSTOP commands.
DATA
SYNCEN
1
Enables the sync pulses at the DATASYNC
output. Each pulse is coincident with the
beginning of the 16-bit data word that cor-
responds to a given output bit.
STRMRST 0
This command resets all the counters irre-
spective of the timing within the stream cycle.
www.maximintegrated.com
Maxim Integrated │ 36
MAX2771 Multiband Universal GNSS Receiver