Hardware Specicaon
User Guide
© 2023 Microchip Technology Inc. and its subsidiaries
DS-50003529B - 90
Figure 10-7. RJ-45 Socket to RJ-11 Connector Pinout
Pin RJ-45 Function Pin RJ-11
1 TMS EJTAG Test Mode Select
2 Reserved 1
3 PGC (ICSPCLK) Standard Com
Clock/TCK (JTAG Test
Clock)
2 PGC (ICSPCLK)
4 PGD (ICSPDAT) Standard Com
Data/TDO (JTAG Test
Data Output)
3 PGD (ICSPDAT)
5 GND Ground 4 GND
6 V
DD
_TGT Power on target 5 V
DD
_TGT
7 V
PP
Power 6 V
PP
8 TDI JTAG Test Data Input
10.6.2 Standard Communicaon
The main interface to the target processor is via standard communication. It contains the
connections to the high voltage (V
PP
), V
DD
sense lines, as well as clock and data connections required
for programming and connecting with the target devices.
The V
PP
high-voltage lines can produce a variable voltage that can swing from 0-14V to satisfy the
voltage requirements of the specic emulation processor.
The V
DD
sense connection draws very little current from the target processor. The actual power
comes from the MPLAB ICD 5 In-Circuit Debugger system, as the V
DD
sense line is used as a
reference only to track the target voltage. The V
DD
connection is isolated with an optical switch.
The clock and data connections are interfaces with the following characteristics:
• Clock and data signals are in high-impedance mode (even when no power is applied to the
MPLAB ICD 5 In-Circuit Debugger system).
• Clock and data signals are protected from high voltages caused by faulty target systems, or
improper connections.
• Clock and data signals are protected from high current caused from electrical shorts in faulty
target systems.