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LCD PC E
LCD PC E
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8590 MAINTENANCE
8590 MAINTENANCE
Connection debounce
Multispeed packet concatenation
Ack accelerated arbitration
Fly-by concatenation
Per port disable, suspend, resume, through register write and remote command packet
Remote access packet
Boundary node short reset
No phy_ID wrap past 63
Provides three 1394a fully compliant cable ports at 100/200/400 Mbit per second
Host notification of PHY LinkOn events
Logic performs bus initialization and arbitration functions
Encode and decode functions included for data-strobe bit-level encoding
Incoming data resynchronized to local clock
24.576 MHz crystal oscillator and PLL provide TX/RX data at 100/200/400 Mbps and Link-Layer Controller
clock at 49.152 MHz
Cable power presence monitoring
Programmable node power class information for system power management
Fully Compliant P1394a 4.0 PHY register map
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