Motorola M68000 - Page 58

5- 12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
GRANT BUS ARBITRATION
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
REQUESTING DEVICE
1) EXTERNAL ARBITRATION DETER-
MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACK)
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
TERMINATE ARBITRATION
1) NEGATE BGACK
PROCESSOR
1) ASSERT BUS GRANT (BG)
ACKNOWLEDGE BUS MASTERSHIP
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ
AND WRITE CYCLES) ACCORDING
TO THE SAME RULES THE PRO-
CESSOR USES
REARBITRATE OR RESUME
PROCESSOR OPERATION
RELEASE BUS MASTERSHIP
1) NEGATE BG (AND WAIT FOR BGACK
TO BE NEGATED)
Figure 5-13. 3-Wire Bus Arbitration Cycle Flowchart
(Not Applicable to 48-Pin MC68008 or MC68EC000)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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