Motorola M68000 - Page 63

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5- 17
RA
XX
RA
RA
RA
XX
R+A
XA
RA
RX
1
1
R = Bus Request Internal
A = Bus Grant Acknowledge Internal
G = Bus Grant
T = Three-state Control to Bus Control Logic
X = Don't Care
Notes:
1. State machine will not change if
the bus is S0 or S1. Refer to
5.2.3.
BUS ARBITRATION CONTROL.
2. The address bus will be placed in
the high-impedance state if T is
asserted and AS is negated.
R
R
R
X
R
X
R
R
(a) 3-Wire Bus Arbitration
(b) 2-Wire Bus Arbitration
GT
GT
GT
GT
RA
RA
RA
RA
XA
RA
GT
RA
GT
GT
GT
GT
GT
GT
GT
STATE 1
STATE 0
STATE 4
STATE 2
STATE 3
Figure 5-18. Bus Arbitration Unit State Diagrams
Figures 5-19, 5-20, and 5-21 applies to all processors using 3-wire bus arbitration. Figures
5-22, 5-23, and 5-24 applies to all processors using 2-wire bus arbitration.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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