Motorola M68000 - Page 64

5- 18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
CLK
BUS THREE-STATED
B
G ASSERTED
B
R VALID INTERNA
L
B
R SAMPLED
B
R ASSERTED
BUS RELEASED FROM THREE STATE AND
P
ROCESSOR STARTS NEXT BUS CYCLE
B
GACK NEGATED INTERNAL
B
GACK SAMPLED
B
GACK NEGATED
BR
BG
BGACK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
ALTERNATE BUS MASTER
PROCESSOR
Figure 5-19. 3-Wire Bus Arbitration Timing Diagram—Processor Active
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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