Motorola M68000 - Page 65

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5- 19
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
CLK
BGACK NEGATED
B
G ASSERTED AND BUS THREE STATED
B
R VALID INTERNAL
B
R SAMPLED
B
R ASSERTED
BR
BG
BGACK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE
PROCESSOR
BUS
I
NACTIVE
ALTERNATE BUS MASTER
Figure 5-20. 3-Wire Bus Arbitration Timing Diagram—Bus Inactive
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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