Motorola M68000 - Page 8

MOTOROLA M68000 USER’S MANUAL xiii
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
5-15 3-Wire Bus Arbitration Timing Diagram
(NA to 48-Pin MC68008 and MC68EC000 ........................................................ 5-13
5-16 2-Wire Bus Arbitration Timing Diagram.............................................................. 5-14
5-17 External Asynchronous Signal Synchronization................................................. 5-16
5-18 Bus Arbitration Unit State Diagrams................................................................... 5-17
5-19 3-Wire Bus Arbitration Timing Diagram—Processor Active ............................... 5-18
5-20 3-Wire Bus Arbitration Timing Diagram—Bus Active ......................................... 5-19
5-21 3-Wire Bus Arbitration Timing Diagram—Special Case ..................................... 5-20
5-22 2-Wire Bus Arbitration Timing Diagram—Processor Active ............................... 5-21
5-23 2-Wire Bus Arbitration Timing Diagram—Bus Active ......................................... 5-22
5-24 2-Wire Bus Arbitration Timing Diagram—Special Case ..................................... 5-23
5-25 Bus Error Timing Diagram.................................................................................. 5-24
5-26 Delayed Bus Error Timing Diagram (MC68010)................................................. 5-25
5-27 Retry Bus Cycle Timing Diagram ....................................................................... 5-26
5-28 Delayed Retry Bus Cycle Timing Diagram......................................................... 5-27
5-29 Halt Operation Timing Diagram.......................................................................... 5-28
5-30 Reset Operation Timing Diagram....................................................................... 5-29
5-31 Fully Asynchronous Read Cycle ........................................................................ 5-32
5-32 Fully Asynchronous Write Cycle......................................................................... 5-33
5-33 Pseudo-Asynchronous Read Cycle ................................................................... 5-34
5-34 Pseudo-Asynchronous Write Cycle.................................................................... 5-35
5-35 Synchronous Read Cycle................................................................................... 5-37
5-36 Synchronous Write Cycle................................................................................... 5-38
5-37 Input Synchronizers ........................................................................................... 5-38
6-1 Exception Vector Format...................................................................................... 6-4
6-2 Peripheral Vector Number Format ....................................................................... 6-5
6-3 Address Translated from 8-Bit Vector Number ................................................... 6-5
6-4 Exception Vector Address Calculation (MC68010).............................................. 6-5
6-5 Group 1 and 2 Exception Stack Frame.............................................................. 6-10
6-6 MC68010 Stack Frame ...................................................................................... 6-10
6-7 Supervisor Stack Order for Bus or Address Error Exception ............................. 6-17
6-8 Exception Stack Order (Bus and Address Error) ............................................... 6-18
6-9 Special Status Word Format .............................................................................. 6-19
10-1 MC68000 Power Dissipation (P
D
) vs Ambient Temperature (T
A
) ..................... 10-3
10-2 Drive Levels and Test Points for AC Specifications ........................................... 10-6
10-3 Clock Input Timing Diagram ............................................................................... 10-9
10-4 Read Cycle Timing Diagram ............................................................................ 10-13
10-5 Write Cycle Timing Diagram............................................................................. 10-14
10-6 MC68000 to M6800 Peripheral Timing Diagram (Best Case).......................... 10-16
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cale Semiconductor,
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