Nvidia JETSON TX2 - Page 49

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 49
Parameter
Requirement
Units
Notes
Min Sdd21 @ 2.5GHz
2.22
dB
Max Scc21 @ 2.5GHz
19.2
dB
Location
Close to any adjacent discontinuity (< 8mm)  such as
connector, via, etc.
ESD (On-chip protection diode is able to withstand 2kV HMM. External ESD is optional. Designs should include ESD footprint as a stuffing option)
Max junction capacitance
(IO to GND)
0.35
pF
e.g. ON-semiconductor ESD8040
Footprint
Pad right on the net instead of trace stub
Location
After pull-down resistor/CMC and before R
S
Void
GND/PWR void under/above the cap is needed. Void
size = 1mm x 2mm for 1 pair
Series Resistor (R
S
)  Series resistor on P/N path for HDMI 2.0 (Mandatory)
Value
 6

± 10%. 0ohm is acceptable if the design passes the
HDMI2.0 HF1-9 test. Otherwise, adjust the R
S
value to
ensure the HDMI2.0 tests pass: Eye diagram, Vlow test
and HF1-9 TDR test
Location
After all components and before HDMI connector
Void
GND/PWR void under/above the R
S
device is needed.
Void size = SMT area + 1x dielectric height keepout
distance.
Trace at Component Region
Value
100

± 10%
Location
At component region (Microstrip)
Trace entering the SMT pad
One 45°
Trace between components
Uncoupled structure
HDMI Connector
Connector Voiding
Voiding the ground below the signal lanes
0.1448(5.7mil) larger than the pin itself
General
Routing over Voids
Routing over voids not allowed except void around device ball/pin the signal is routed to.
Noise Coupling
Keep critical HDMI related traces including differential clock/data traces & RSET trace away from other signal
traces or unrelated power traces/areas or power supply components
Note:
1. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the
max trace lengths will need to be reduced.
2. The average of the differential signals is used for length matching.
3. Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before vias or
any discontinuity to minimize common mode conversion
4. If routing includes a flex or 2
nd
PCB, the max trace delay & skew calculations must include all the PCBs/flex routing.
Solutions with flex/2
nd
PCB may not achieve maximum frequency operation.