Nvidia JETSON TX2 - Page 98

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 98
Pin #
Module Pin Name
Tegra Signal
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
C33
GND

GND
GND

GND
C34
DSI1_D0+
DSI_B_D0_P
Display, DSI 1 Data 0+
Display Connector
Output
MIPI D-PHY
C35
DSI1_D0
DSI_B_D0_N
Display, DSI 1 Data 0
Output
C36
GND

GND
GND

GND
C37
DP1_TX1
HDMI_DP1_TXDN1
DisplayPort 1 Lane 1 or HDMI Lane 1
HDMI Type A Conn.
Output
AC-Coupled on carrier
board
C38
DP1_TX1+
HDMI_DP1_TXDP1
DisplayPort 1 Lane 1+ or HDMI Lane 1+
Output
C39
GND

GND
GND

GND
C40
PEX2_TX+
PEX_TX3P
PCIe 2 Transmit+ (PCIe IF #0 Lane 2 or
PCIe IF #1 Lane 0)
PCIe x4 Connector
Output
PCIe PHY, AC-Coupled on
carrier board
C41
PEX2_TX
PEX_TX3N
PCIe 2 Transmit (PCIe IF #0 Lane 2 or
PCIe IF #1 Lane 0)
Output
C42
GND

GND
GND

GND
C43
USB_SS0_TX+
PEX_TX0P
USB SS 0 Transmit+ (USB 3.0 Port #0
muxed w/PCIe #2 Lane 0)
USB 3.0 Type A
Output
USB SS PHY, AC-Coupled on
carrier board
C44
USB_SS0_TX
PEX_TX0N
USB SS 0 Transmit (USB 3.0 Port #0
muxed w/PCIe #2 Lane 0)
Output
C45
GND

GND
GND

GND
C46
PEX2_CLKREQ#
PEX_L1_CLKREQ_N
PCIE 2 Clock Request (PCIe IF #1)
Unassigned
Bidir
Open Drain 3.3V, Pull-up on
the module
C47
PEX1_CLKREQ#
PEX_L2_CLKREQ_N
PCIE 1 Clock Request (mux option - PCIe
IF #2)
M.2 Key E
Bidir
C48
PEX0_CLKREQ#
PEX_L0_CLKREQ_N
PCIE 0 Clock Request (PCIe IF #0)
PCIe x4 Connector
Bidir
C49
PEX0_RST#
PEX_L0_RST_N
PCIe 0 Reset (PCIe IF #0)
Output
C50
RSVD

Not used



D1
RSVD

Not used



D2
RSVD

Not used



D3
RSVD

Not used



D4
RSVD

Not used



D5
UART7_RX
UART7_RX
UART 7 Receive
Not Assigned
Input
CMOS  1.8V
D6
I2C_CAM_DAT
CAM_I2C_SDA
Camera I2C Data
Camera Connector
Bidir
Open Drain  1.8V
D7
GPIO5_CAM_FLASH_EN
UART5_RTS_N
Camera Flash Enable or GPIO
Output
CMOS  1.8V
D8
UART7_TX
UART7_TX
UART 7 Transmit
Not Assigned
Output
CMOS  1.8V
D9
UART1_TX
UART3_TX
UART 1 Transmit
Serial Port Header
Output
CMOS  1.8V
D10
UART1_RX
UART3_RX
UART 1 Receive
Input
CMOS  1.8V
D11
RSVD

Not used



D12
RSVD

Not used



D13
I2S1_LRCLK
DAP2_FS
I2S Audio Port 1 Left/Right Clock
GPIO Expansion
Header
Bidir
CMOS  1.8V
D14
I2S1_SDOUT
DAP2_DOUT
I2S Audio Port 1 Data Out
Bidir
CMOS  1.8V
D15
I2C_GP0_DAT
GPIO_SEN9
General I2C 0 Data
I2C (General)
Bidir
Open Drain  1.8V
D16
AO_DMIC_IN_DAT
CAN_GPIO0
Digital Mic Input Data
GPIO Expansion
Header
Input
CMOS  1.8V
D17
CAN1_RX
CAN1_DIN
CAN 1 Receive
Input
CMOS 3.3V
D18
CAN0_RX
CAN0_DIN
CAN 0 Receive
Input
CMOS 3.3V
D19
CAN0_TX
CAN0_DOUT
CAN 0 Transmit
Output
CMOS 3.3V
D20
GND

GND
GND

GND
D21
CSI5_CLK
CSI_F_CLK_N
Camera, CSI 5 Clock
Camera Connector
Input
MIPI D-PHY
D22
CSI5_CLK+
CSI_F_CLK_P
Camera, CSI 5 Clock+
Input
D23
GND

GND
GND

GND
D24
CSI3_CLK
CSI_D_CLK_N
Camera, CSI 3 Clock
Camera Connector
Input
MIPI D-PHY
D25
CSI3_CLK+
CSI_D_CLK_P
Camera, CSI 3 Clock+
Input
D26
GND

GND
GND

GND
D27
CSI1_CLK
CSI_B_CLK_N
Camera, CSI 1 Clock
Camera Connector
Input
MIPI D-PHY
D28
CSI1_CLK+
CSI_B_CLK_P
Camera, CSI 1 Clock+
Input
D29
GND

GND
GND

GND
D30
DSI3_CLK+
DSI_D_CLK_P
Display DSI 3 Clock+
Display Connector
Output
MIPI D-PHY
D31
DSI3_CLK
DSI_D_CLK_N
Display DSI 3 Clock
Output
D32
GND

GND
GND

GND
D33
DSI1_CLK+
DSI_B_CLK_P
Display DSI 1 Clock+
Display Connector
Output
MIPI D-PHY
D34
DSI1_CLK
DSI_B_CLK_N
Display DSI 1 Clock
Output
D35
GND

GND
GND

GND
D36
DP1_TX2
HDMI_DP1_TXDN0
DisplayPort 1 Lane 2 or HDMI Lane 0
HDMI Type A Conn.
Output
AC-Coupled on carrier
board
D37
DP1_TX2+
HDMI_DP1_TXDP0
DisplayPort 1 Lane 2+ or HDMI Lane 0+
Output
D38
GND

GND
GND

GND
D39
PEX_RFU_TX+
PEX_TX1P
PCIe RFU Transmit+ (PCIe IF #0 Lane 3 or
USB 3.0 Port #1)
PCIe x4 Connector
Output
PCIe PHY, AC-Coupled on
carrier board