NXP Semiconductors MPC5777M - LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical characteristics

Safety Manual for MPC5777M, Rev. 1.1
Address decoding coverage
NXP Semiconductors66
GTM
FIFO1,2
not mandatory
application
dependent
8 1024 36 12 A<11:9> A<8:7> A<6:5> A<4:3> A<2:0> —
(MCSi)-RA
M0, i=0-2...6
not mandatory
application
dependent
8 1024 39 12 A<11:9> A<8:7> A<6:5> A<4:3> A<2:0> —
(MCSi)-RA
M1, i=0-2...6
not mandatory
application
dependent
4 512 39 10 — A<9:7> A<6:4> A<3:2> A<1:0> —
DPLL-1A
not mandatory
application
dependent
4 128 31 10 — A<9:7> A<6:4> A<3:2> A<1:0> —
DPLL-1B
not mandatory
application
dependent
4 384 31 10 — A<9:7> A<6:4> A<3:2> A<1:0> —
DPLL-2
not mandatory
application
dependent
16 4096 31 13 A<12:10> A<9:8> A<7:6> A<5:4> A<3:0> —
NOTES:
1
Internal data memory of Core_0 (and Core_1) is implemented by 2 separated memory instantiations, i.e. D-Mem0 and D-Mem1. Such memories are connected
in parallel. Considering a 64bit word, the first 32bit are located in D-Mem0 and the second 32bit in D-Mem1. Each memory has its own decoding logic. In case
of single bit error correction, the self-test to detect failure in the addressing logic shall be executed only in the memory in which the error is detected, either
D-Mem0 or D-Mem1.
Table 4. Address decoding (continued)
Word address predecoding bits
Row selection
Column
selection
Location Memory
Shall be
tested?
Mux
Number of
words
Bits
per
word
Number
of
address
bits
Dec D Dec C Dec B Dec A Dec E
Block
address