Address decoding coverage
Safety Manual for MPC5777M, Rev. 1.1
NXP Semiconductors 67
Table 4 reports multiple details about the design of each RAM impacted by the described software
self-test. Details below must be used to implement the testing algorithm:
•Muxing
• Number of words for the whole array
• Bits per words
• Number of address bits
• Number of bits used as address by the RAM
• Info about decoder addressing structure in terms of multiplexer
— testing algorithm is based on several reading of different RAM locations; list of these locations
depends on the decoding structure of the RAM.
During each memory access operation, the word is selected via multiple decoders connected to the RAM
cells. How the address bus is decoded for the memory array depends on the design parameters described
in Table 4.
The address bus is partitioned to:
• Row decoders (for example,. DecD, DecC, DecB and DecA)
— these bits are used to select the row to be accessed
• Column decoders (for example, DecA)
— these bits are used to select the column to be accessed
• Block selection (for example, block address)
— these bits are used to select the block to be accessed in case the memory is internally partitioned
in multiple blocks.
Let’s assume a permanent failure in the addressing logic causes an MBE. This MBE may be incorrectly
interpreted as single bit error by the ECC/EDC hardware. The address of the reported single bit error is
indicated as Ah
1
.
To distinguish this permanent addressing fault from an SBE, some back-to-back reads from Ah and their
coupled addresses shall be executed.
Considering the hit address as starting point, the self-test requires reading a list of locations correlated in
some way to hit address.
This list includes different locations whose address is obtained by changing one by one the bits of each
decoding group (DecD, DecC, and so on).
All these memory locations shall be read following a specific order as described below.
Table 5 (Example of back-to-back read to implement test) reports an example of list of addresses obtained
starting from a specific hit address (also called victim).
This example assumes a single bit error reported at the hit address Ah of the SRAM. With reference to
Table 1, the addressing logic of the system RAM consists of 13 bits which go through multiple decoders:
• Row selection
1.Hitting address.
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