Renesas TPS-1 User Manual

TPS-1 User’s Manual: Hardware 4. Shared memory structure
R19UH0081ED0107 Rev. 1.07 page 41 of 86
Jul 30, 2018
One or more bits written in to these registers (*_low and *_high) process an external interrupt event (INT_OUT). A new one will influence no bits set
before.
Table 4-6: Register Host_IRQmask_low
Name
Host_IRQmask_low
Address 0x0010
Access
r/w
Bits Type of Event Description Init:
31:00
IRQ –Bits
“0”: the Event is registered in PN_Event_low
“1”: the Event is not registered in PN_Event_low
0xFFFFFFFF
Table 4-7: Register Host_IRQmask_high
Name
Host_IRQmask_high
Address 0x0014
Access
r / w
Bits Type of Event Description Init:
31:00
IRQ –Bits
“0”: the Event is registered in PN_Event_high
“1”: the Event is not registered in PN_Event_high
0xFFFFFFFF
After processing an event, the corresponding bit must be acknowledged by writing of acknowledgment register Host_IRQack_low and
Host_IRQack_high.
Table 4-8: Register Host_IRQack_low
Name
Host_IRQack_low
Address 0x0020
Access
- / w
Bits Type of Event Description Init:
31:00
Ack –Bits
“0”: the Event-Bit is not deleted in PN_Event_low
“1”: the Event-Bit is deleted in PN_Event_low
-
Table 4-9: Register Host_IRQack_high
Name
Host_IRQack_high
Address
0x0024
Access - / w
Bits
Type of Event
Description
Init:
31:00
Ack –Bits
“0”: the Event-Bit is not deleted in PN_Event_high
“1”: the Event-Bit is deleted in PN_Event_high
-

Renesas TPS-1 Specifications

General

Brand	Renesas
Model	TPS-1
Category	Controller
Language	English