SICK MITSUBISHI ELECTRIC MELSEC iQ-F Series - Page 144

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APPX
Appendix 5 Buffer Memory
Output signals and module status
The information on the output terminals of a module and the statuses of each function are stored.
■Buffer memory address
The buffer memory address of this area is as follows.
■Output signals and statuses of each function
FX5-SF-MU4T5
FX5-SF-8DI4
Buffer memory name Address
1st Module Output signal and Module state 101
2nd Module Output signal 141
3rd Module Output signal 181
Bit Output terminal or function of
FX5-SF-MU4T5
Operation
b0 Output signal Q0 0: No output
1: Output
b1 Output signal Q1
b2 Output signal Q2
b3 Output signal Q3
b4 X0 restart interlock reset request 0: No reset request
1: Reset request
b5 X1 restart interlock reset request
b6 Muting function 0: Inactive
1: Active
b7 Bypass function 0: Inactive
1: Active
b8 to b15  Fixed to 0
Bit Output terminal or function of
FX5-SF-8DI4
Operation
b0 
b1 Output signal QA 0: No output
1: Output
b2 
b3 Output signal QB 0: No output
1: Output
b4 
b5 
b6 
b7 
b8 to b15  Fixed to 0