Siemens S5-100U - Explanation of the Mnemonics Used in ISTACK

S5-100U Diagnostics and Troubleshooting
5.2.4 Explanation of the Mnemonics Used in “ISTACK”
Table 5-5. Meaning of the Remaining ISTACK Bits
*
relevant for CPU 103 only
** for CPU 102: 0 = normal mode
1 = test mode
ISTACK
Display
Byte Explanation
BST SCH
SCH TAE
ADR BAU
1 Shift block.
Execute shift operation.
Structure address list.
FKT 13 0: O( OR parenthesis open
1: A( AND parenthesis open
STO ANZ
STO ZUS
BAT PUF
NEU STA
3 PLC in STOP
Internal control bit for STOP/RUN change
Battery backup available
PLC not yet in cycle after Power ON
- See bytes 9 and 10 for cause.
AF* 4 Interrupt enable/enabling of time-controlled OB13 and interrupt-
driven OB3
KOPFNI 5 Program contains errors.
Block header cannot be interpreted.
KEIN AS**
URLAD
SYNFEH
6 Not enough S5 statement memory available
Overall reset, program defective
Program contains errors.
ANZ 1/ANZ 0
OV
OR
STATUS
VKE
ERAB
12 Condition code bits for arithmetic, logic, and shift operations.
Arithmetic overflow
ID bit of OR memory
Status ID of operand of last binary statement executed
Result of logic operation (RLO)
ID bit of first scan
EWA 4NEB 812 6120-02 5-7