Siemens SPC3 - Page 26

PROFIBUS Interface Center SPC3
Page 24 V1.3 SPC3 Hardware Description
2003/04 Copyright (C) Siemens AG 2003. All rights reserved.
The other interrupt controller registers are assigned in the bit positions, like the IRR.
Address Register Reset State Assignment
02H /
03H
Interrupt Register
(IR)
Readable
only
All bits deleted
04H /
05H
Interrupt Mask
Register
(IMR)
Writable, can
be changed
during
operation
All bits set Bit =
1
Bit =
0
Mask is set and the interrupt
is disabled.
Mask is deleted and the
interrupt is enabled.
02H /
03H
Interrupt
Acknowledge
Register
(IAR)
Writable, can
be changed
during
operation
All bits deleted Bit =
1
Bit =
0
The IRR bit is deleted.
The IRR bit remains
unchanged.
Figure 5.5: Additional Interrupt Registers
The ‘New_Prm_Data’, ‘New_Cfg_Data’ inputs may not be deleted via the Interrupt Acknowledge Register.
The relevant state machines delete these inputs through the user acknowledgements (for example,
‘User_Prm_Data_Okay’ etc.).