Siemens SPC3 - Timing in the Synchronous C32-Mode

SPC3 PROFIBUS Interface Center
SPC3 Hardware Description V1.3 Page 47
Copyright (C) Siemens AG 2003 All rights reserved. 2003/04
Reset:
SPC3 requires a minimum of 400 clock pulse cycles during the reset phase so that it can be reset correctly.
Reset
8.5.2 Timing in the Synchronous C32-Mode:
If SPC3 is operated at 48MHz, an 80C32 with a maximum clock pulse rate of 20MHz can be connected.
In the C32 mode, SPC3 saves the least significant addresses with the negative edge of ALE. At the same
time, SPC3 expects the more significant address bits on the address bus. SPC3 generates a chipselect
signal from the more significant address bits. The request for an access to SPC3 is generated from the
negative edge of the read signal and from the positive edge of the write signal.
AMI-Vers.
ST-Vers.
No. Parameter Min Max Min Max Unit
1
Address to ALE ↓ Setuptime
10
10
ns
2
Address (AB
8..15
) Holdtime after XRD ↑ or XWR ↑
5
5
ns
3
XRD ↓ to Data Out (Zugriff auf RAM)
4T + 5
(88,3)
3T+42.5
(105)
ns
XRD ↓ to Data Out (Zugriff auf die Register)
4T + 18
(101,3)
4T+20.2
(103,5)
ns
4
ALE ↓ to XRD ↓
20
20
ns
5
Data Holdtime after XRD ↑
2 6
3.1 10.2
ns
6
Data Holdtime after XWR ↑
10
10
ns
7
Data Setuptime to XWR ↑
10
10
ns
8
XRD ↑ to ALE ↑
10
10
ns
10 XRD-Pulse-Width 6T - 10
6T
− 10
ns
11 XWR-Pulse-Width 4T
4T
ns
12
Address-Holdtime after ALE ↓
10
10
ns
13 ALE-Puls-Width 10
10
ns
14 XRD, XWR Cycletime 6T + 30
6T + 30
ns
15
ALE ↓ to XWR ↓
20
20
ns
16
XWR ↑ to ALE ↑
10
10
ns
Explanations:
T = Clock pulse cycle (48MHz)
TBD = to be defined
(1
= Access to the RAM
(2
= Access to the registers/latches
(3)
= for T = 48MHz