Siemens SPC3 - Timing in the Asynchronous Motorola-Mode (for Example, 68 HC16)

PROFIBUS Interface Center SPC3
Page 52 V1.3 SPC3 Hardware Description
2003/04 Copyright (C) Siemens AG 2003. All rights reserved.
Synchronous Motorola-Mode, Processor-Write-Timing
R_W
VALID
Data Valid
AB(10..0)
DB(7..0)
XCS
AS = log.'1'
E_Clock
41
40
42
46
50 51
47
49
48
8.5.5 Timing in the Asynchronous Motorola-Mode (for example, 68HC16) :
In the asynchronous Motorola mode, the SPC3 acts like memory with Ready logic, whereby the access
times depend on the type of accesses.
The request for an access of SPC3 is generated from the positive edge of the AS signal (in addition:
XCS=´0´, R_W=´1´). The request for a write access is generated from the positive edge of the AS signal (in
addition: XCS=´0´, R_W=´0´).
AMI-Vers.
ST-Vers.
No. Parameter Min Max Min Max Unit
60
Address-Setuptime to AS ↓
0
0
ns
61
AS ↓ to Data valid (Zugriff auf RAM)
4T + 5
(88,3)
3T + 45.2
(108)
ns
AS ↓ to Data valid (Zugriff auf die Register)
4T + 18
(101,3)
4T + 22.9
(106,2)
ns
62
Address (AB
10..0
) Holdtime after AS ↑
10
10
ns
63
R_W ↓ Setuptime to AS ↓
10
10
ns
64 AS-Puls-Width (Read) 6T - 10
6T
− 10
ns
65
Data Holdtime after AS ↑
2 6.3
4 12
ns
66 AS-Inactive-Time 10
10
ns
67
R_W Holdtime after AS ↑
10
10
ns
68
XCS ↓ Setuptime to AS ↓
-5
-5
ns
69
XCS Holdtime after AS ↑
0
0
ns
70
AS ↓ to XDSACK ↓ (Read, Normal Ready)
4T + 5 5T + 14
5T + 16
ns
71
AS ↓ to XDSACK ↓ (Read, Early Ready)
3T + 5 4T + 14
4T + 16
ns
72
XDSACK-Holdtime after AS ↑
4.3 12.7
6 22
ns
73 AS Cycletime 6T
6T
ns
74
Data Setuptime to AS ↑
10
10
ns
75
Data Holdtime after AS ↑
10
10
ns
76 AS-Pulse-Width (Write) * 4T
4T
ns
77
last AS
 (Read) to XCS 
4T + 10
4T + 10
ns
78
XCS
 to next AS  (Write)
2T + 10
2T + 10
ns
79
AS
 to next AS  (Write, XCS don’t care)
6T
6T
ns
Explanations: