Siemens SPC3 - Page 55

SPC3 PROFIBUS Interface Center
SPC3 Hardware Description V1.3 Page 53
Copyright (C) Siemens AG 2003 All rights reserved. 2003/04
T = Pulse cycle (48MHz)
TBD = To Be Defined
(1
= Access to the RAM
(2
= Access to the register/latches
(3
= For T = 48MHz
Asynchronous Motorola-Mode, Processor-Read-Timing
AS
VALID
Data Out
AB(10..0)
DB(7..0)
R_W
E_Clock = log.'0'
63
70
62
65
61
64
XDSACK
(normal)
XDSACK
(early)
67
72
60
71
66
73
69
XCS
6877
Asynchronous Motorola-Mode, Processor-Write-Timing
AS
VALID
AB(10..0)
DB(7..0)
E_Clock = log.'0'
63
62
75
76
74
Data In
R_W
XDSACK
(normal)
67
72
70
60
66
69
XCS
68
71
73
XDSACK
(early)
78
79