Sony SSC-DC593 - Page 47

5-7
SSC-DC593/DC593P/DC598P (E)
DEFECT
COMPENSATION
DEFECT
DETECTION
OPB
INTEGRATION
49
VCK/SCK
CBAR GEN.
SG
SYNC GEN.
SYNC SEP.
1HDL
1HDL
H APERTURE CONT.
V APERTURE CONT.
LPF
CLP
OPDY OPDC
γ
NR
Y SIGNAL PROCESSOR
YDL
YO0 - YO7
YI0 - YI7
CHARM
CHARB
VGATE
CO0 - CO3
MEMCID
COUT
YOUT
CI0 - CI3
SFC ENC DAC
DAC
VARIABLE
γ
RGB
MATRIX
HIGHLIGHT
APERTURE
CONT.
Y GAIN
γ
HUE
GAIN
C SIGNAL PROCESSOR
LPF
CLP
AE
DETECTOR
AWB
DETECTOR
ZOOM MEMORY
I/F
71
MCK
27
I4FSC
40
XCLR
18
XSG1/SIN
20
XV1
64 - 65
10
1H
0+2H
D0 - D9
3
PBLK
47
54
53
65
45
44
67
31
18
23
29
22
30
LID
34
EXTSYNCI
TGHD
TGVD
CLPOB
HDO
VDO
FLDO
SYNCO
FSCO
SCGATE
PHASE COMP.
35
EXTVDI
PLLHV
33
EXTSCI
PLLHVEN
32
FSCI
SIO
38
36
46
13
12
79 - 77
69
83 - 80
XSCE
37
SI
SO
39
XSCK
PLLSC
8 8
99 - 91
90 - 84
41
42
4
4
x
+
+
++
LB1940U-TLM-E (SANYO)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VS1 IN
SV CC OUT
V CC
OUT1 OUT
RFG1 OUT
OUT2 OUT
OUT3 OUT
RFG2 OUT
OUT4 OUT
VS2 IN
VC1 IN
S-GND OUT
VC2 IN
Vref OUT
ENA1 IN
ENA2 IN
IN1 IN
IN2 IN
FC1 OUT
FC2 OUT
H BRIDGE MOTOR DRIVER
—TOP VIEW—
INPUTS
ENA1, ENA2
IN1, IN2
VC1, VC2
VS1, VS2
OUTPUTS
FC1, FC2
OUT1 - OUT4
RFG1, RFG2
SV
CC , S-GND
: CONTROL SIGNAL
: REFERENCE VOLTAGE FOR CONTROL
: POWER SUPPLY FOR MOTOR
: PHASE COMPENSATION CAPACITOR
CONNECTION TERMINAL
: MOTOR DRIVE
: CONSTANT-CURRENT DETECTION
: POWER SUPPLY OUTPUT FOR CONTROL
SYSTEM
1
0
1
x
x
1
2
0
1
x
1
0
x
x
2
x
x
x
1
0
WAITING
1ch REVERSE ROTATION
1ch NORMAL ROTATION
2ch REVERSE ROTATION
2ch NORMAL ROTATION
0
1
x
: LOW LEVEL
: HIGH LEVEL
: DON'T CARE
1
x
0
1
x
x
2
x
1
0
x
x
3
x
x
x
0
1
4
x
x
x
1
0
INPUTS OUTPUTS
MODE
SV
CC
ENA IN OUT
OFF
ON
ON
ON
ON
REFERENCE VOLAGE
LOGIC CIRCUIT
65k 80k
+
_
+
_
65k 80k
65k 80k
65k 80k
V CC -SW
VC1 VS1
OUT1
OUT2
V
CC
Vref
OUT3
OUT4
VS2
VC2
S-GND
SVcc
FC1
FC2
RFG1 ENA1
ENA2
IN1
IN2
RFG2
1
2 3
4
5
6 7
8
9
10
11
12
13 14 15 16
17
18
19
20
300Z
300Z
IC