ST STEVAL-WBC2TX50 - Figure 43. Setup for Offset Test; Figure 44. X-Axis Offset Impact on Efficiency

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Figure 43. Setup for offset test

The maximum efficiency achieved with this setup was 85.25%.

Efficiency curves for various misalignments in the X and Y axis are shown in the figures below:

Figure 44. X-axis offset impact on efficiency

UM3231

STEVAL-WBC2TX50 description

UM3231 - Rev 1

page 61/84

Main Page

Figure 1. STEVAL-WBC2TX50 Evaluation Board1
Getting Started2
Reference Design Specifications3
Table 1. Reference Design Specifications3
Overview of the Board4
Figure 2. Board Overview4
Test Points6
Figure 3. Test Points6
Table 2. Test Points6
Basic Operating Modes7
Status Leds7
Table 3. Status Leds Meaning7
Device Description and Operation8
System Block Diagram8
Power Inverter8
Adc8
Figure 4. Block Diagram8
Bridge Voltage Monitor9
DC-DC Current Monitor9
Bridge Current Monitor9
Ring Voltage Monitor9
Onboard Voltage Sources9
DC-DC Buck Converter9
The 3.3 V LDO9
The 1.8 V LDO9
Voltage Doubler9
Power up Sequence10
Uvlo10
Chip Reset10
Protections Overview10
Main Overcurrent Protection (OCP)10
Overvoltage Protection (OVP)10
Voltage Drop11
RX Overvoltage Protection - Static/Dynamic OVP, Currentdrop OVP11
Overtemperature Protection (OVTP)11
Ntc11
Qfod11
Foreign Object Detection (FOD)11
Presence Detection11
Comparing to Reference Q Factor12
Power Balance12
EPT Reason12
WPC Qi Wireless Power Transfer12
Baseline and Extended Power Profiles12
Figure 5. Difference between BPP and EPP Power Transfer Startup13
Wireless Power Interface14
Bidirectional Communication14
ASK Communication14
Figure 6. ASK Modulation15
Figure 7. ASK Timing15
Figure 8. Example of Bit Encoding15
FSK Communication16
Figure 9. Example of Byte Encoding16
Most Common Qi Communication Packets17
Figure 10. Format of the Three Defined Messages17
Stlink18
STLINK Drivers18
Stm32Cube Programmer18
Firmware Flash Programming19
Figure 11. STLINK Parameters19
Figure 12. Programming the Chip19
Uart20
UART Configuration20
Firmware Update Without GUI20
Figure 13. Bootloader Start20
Table 4. Switch to Boot Mode21
Table 5. Init in Bootloader21
Table 6. Get Command21
Table 7. Memory Erase Command22
Table 8. Memory Write Command22
Bootloader and Boot Pin23
Stsafe23
STSAFE-A110 for Qi Authentication23
Table 9. Calibration Command23
The Qi Authentication Procedure24
Figure 14. the Certificate Chain Process24
Figure 15. the Authentication Process24
STSAFE-A110 Test Profile for STEVAL-WBC2TX5025
Table 10. STSAFE-A110 Certificate Chain Elements25
How to Acquire Official STSAFE-A110 Samples26
Fan Support26
Graphical User Interface (GUI)27
Connecting STWBC2 to the GUI27
Figure 16. the Initial State of the GUI27
Info Page28
Status Semaphore28
Figure 17. Port Selection28
Figure 18. Status Semaphore28
Event Box29
Figure 19. Event Box29
Table 11. Available Events30
Device Metrics33
Figure 20. Device Metrics33
Figure 21. Input Power Supply Indication33
Tx Information35
Rx Information35
Figure 22. Device Information35
Figure 23. Rx Identification Data35
Charts Page36
Chart Controls and Shortcuts36
Parameters Page36
Figure 24. Example of Captured Charts36
Table 12. Chart Controls and Shortcuts36
Configuration File37
Device Parameters37
Figure 25. Save and Load Buttons37
Table 13. List of Configurable Parameters37
Read/Write to Device40
Traces Page40
Using Traces for FOD Tuning Data Collection40
Figure 26. Read and Write Operation Buttons40
Figure 27. Save Button, Choosing of Saved Data Type and Save Dialog40
FW Page41
Obtaining the Firmware Update File41
Loading the Firmware into an Empty Device41
Updating Firmware of a Previously Programmed Device41
Calibration41
Recommended Flow of Prototyping and Production42
Protection Tuning42
Foreign Object Detection42
Static OVP42
Figure 28. Test Points42
Dynamic OVP43
Current Drop OVP43
Ring Node Overvoltage43
STEVAL-WBC2TX50 Description44
Schematic Diagrams44
Figure 29. STEVAL-WBC2TX50 Circuit Schematic (1 of 6)44
Figure 30. STEVAL-WBC2TX50 Circuit Schematic (2 of 6)45
Figure 31. STEVAL-WBC2TX50 Circuit Schematic (3 of 6)46
Figure 32. STEVAL-WBC2TX50 Circuit Schematic (4 of 6)47
Figure 33. STEVAL-WBC2TX50 Circuit Schematic (5 of 6)47
Figure 34. STEVAL-WBC2TX50 Circuit Schematic (6 of 6)48
Bill of Materials (BOM)49
Table 14. STEVAL-WBC2TX50 BOM49
Component Assembly54
Figure 35. Component Assembly54
STEVAL-WBC2TX50 PCB Layout55
Figure 36. PCB Top Layer55
Figure 37. PCB Inner1 Layer55
Figure 38. PCB Inner2 Layer56
Figure 39. PCB Bottom Layer56
STWBC2 Default Configuration57
Table 15. Basic Parameters57
Typical Performance Characteristics58
Power-Up Waveforms58
Figure 40. Device Power up58
Analog and Digital Ping59
Figure 41. Analog and Digital Ping59
Startup of EPP60
Efficiency and Spatial Freedom in the XY Plane60
Figure 42. Startup of EPP60
Figure 43. Setup for Offset Test61
Figure 44. X-Axis Offset Impact on Efficiency61
Efficiency and Spatial Freedom in the Z-Axis62
Figure 45. Y-Axis Offset Impact on Efficiency62
Figure 46. Z-Axis Offset Impact on Efficiency62
Thermal Performance63
Figure 47. Thermal Performance63
Designing a Wireless Power Transmitter Based on STEVAL-WBC2TX5064
Evaluation Board64
BOM Reduction Suggestions64
Layout Guidelines64
High Power Tracks64
Figure 48. Layer 1 High Power Tracks64
Ground Plane on Layer 465
Figure 49. Layer 4 GND65
Board Input Layout66
Figure 50. Placement of Input Connectors, Filtering, and Protections66
VIN, Vbuck, and Vdoubler67
Figure 51. Larger Tracks of DC-DC Buck, VIN67
Figure 52. Green: DC-DC Buck Placement. Yellow: Capacitors Close to STWBC2 IC68
VIN ISNS Routing69
Figure 53. VIN ISNS Routing69
DC-DC Boost Circuit70
Main Bridge Circuit70
Figure 54. DC-DC Boost Circuit Routing70
Figure 55. Main Bridge Circuit70
Bridge ISNS Routing71
Gate Drivers Routing71
DC-DC Short Circuit71
Q Factor Driver71
Figure 56. Bridge ISNS Routing71
Figure 57. DC-DC Short Path through Q40471
Board Versions72
Table 16. STEVAL-WBC2TX50 Versions72
Regulatory Compliance Information73
References74
Acronyms and Definition75
Table 17. List of Acronyms75
Revision History76
Table 18. Document Revision History76

ST STEVAL-WBC2TX50 - Figure 43. Setup for Offset Test; Figure 44. X-Axis Offset Impact on Efficiency

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