ST STM8S Application Note

Reference design AN2752
20/42 Doc ID 14651 Rev 3
7.2 Schematics
Figure 11. Reference design
1. If pins 22 or 25 are required as GPIO, R1 and R2 should be removed.
2. V
DD
must be within the allowed supply voltage range of the STM8S microcontroller.
1
4
3
2
B1
C1
100 nF
C3
20 pF
C2
20 pF
X1
24 MHz
C4
470 nF
PA1
PA2
C9
1 µF
VDD 2)
PF1
PF2
PA0
VCAP
C5
100 nF
C6
100 nF
C7
100 nF
NRST
1
PA1/OSCIN
2
PA2/OSCOUT
3
VSSIO_1
4
VSS
5
VCAP
6
VDD
7
VDDIO_1
8
PA3/TIM2_CH3[TIM3_CH1]
9
PA4/UART1_RX
10
PA5/UART1_TX
11
PA6/UART1_CK
12
PH0
13
PH1
14
PH2
15
PH3
16
PF7/AI N15
17
PF6/AI N14
18
PF5/AI N13
19
PF4/AI N12
20
PF3/AI N11
21
PF2/VREF +
22
VDDA
23
VSSA
24
PF1/VREF -
25
PF0/AI N10
26
PB7/AIN7
27
PB6/AIN6
28
PB5/AIN5[I2C_SDA]
29
PB4/AIN4[I2C_SCL]
30
PB3/AIN3[TIM1_ETR]
31
PB2/AIN2[TIM1_CH3N]
32
PB1/AIN1[TIM1_CH2N]
33
PB0/AIN0[TIM1_CH1N]
34
PH4/TI M1_ETR
35
PH5/TIM1_CH3N
36
PH6/TIM1_CH2N
37
PH7/TIM1_CH1N
38
PE6/AIN9
39
PE7/AIN8
40
PE5/SPI_NSS
41
PC0/ADC_ ETR
42
PC1/TIM1_CH1
43
PC2/TIM1_CH2
44
PC3/TIM1_CH3
45
PC4/TIM1_CH4
46
PC5/SP I _SCK
47
VSSIO_2
48
VDDI O_2
49
PC6/SP I_MOSI
50
PC7/SP I_MI SO
51
PG0/CAN_TX
52
PG1/CAN_RX
53
PG2
54
PG3
55
PG4
56
PI0
57
PI1
58
PI2
59
PI3
60
PI4
61
PI5
62
PG5
63
PG6
64
PG7
65
PE4
66
PE3/TIM1_BKI N
67
PE2/I 2C_SDA
68
PE1/I 2C_SCL
69
PE0/CLK_CCO
70
PI6
71
PI7
72
PD0/TIM3_CH2[TIM1_BKIN][CLK_CCO]
73
PD1/SWIM
74
PD2/TIM3_CH1[TIM2_CH3]
75
PD3/TIM2_CH2[ADC_ETR]
76
PD4/TIM2_CH1[BEE P]
77
PD5/UART3_TX
78
PD6/UAR T3_RX
79
PD7/TL I[TIM1_CH4]
80
U1 STM8 Package L QF P 80- pin
1
2
3
4
CN1
SW IM connector
Debug
VDD 2)
R2 0
0R1 0
C8
100 nF
VDD
VDD 2)
MCU
Decoupling Capacitor
Clock(H SE )
R eset
1)
2)
ai15471B
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English