Synchronization with distributed clocks
Operation manual
ID 441896.05
WE KEEP THINGS MOVING
43
9
The parameter G95 shows the status of the PLL regulation
1. Bit 0 and/or bit 1 not 0: The cycle time of the SYNC0 signal must be a whole-
number multiple of the inverter cycle time A150. Set the cycle time of the
SYNC0 signal in the master to a whole-number multiple of A150.
2. Bit 4 = 1: The measured cycle time is greater than the one specified. The cycle
time of the SYNC0 signal must be a whole-number multiple of the inverter
cycle time A150. Set the cycle time of the SYNC0 signal on the master to a
whole-number multiple of A150.
3. Bit 5 = 1: PLL regulation is deactivated. Check whether PLL regulation was
deactivated manually in G90.
If these defect descriptions do not help you further, or if you want optimally adjust
the phase offset of the internal PLL to your application, contact us with a case
description on
• The telephone number +49 (0) 7231 582-1187 or
• "The e-mail address applications@stoeber.de
Cyclic process data communication with EtherCAT is based on a telegram which
is passed along to all slaves. Due to the signal runtime of the telegram, the
connected slaves are provided with the reference values at different times.
The concept of distributed clocks (DC) is used to synchronize the slaves with the
master. Each slave has a high-precision clock with its own time base. After these
clocks are calibrated by the master with a reference clock, they continue running
synchronously by themselves. Due to the ring structure of the network, the
differences in runtime can be measured and taken into consideration when the
clocks are calibrated.
A total of three times are taken into consideration for the calibration and set on the
master:
• The Master Shift Time is the telegram runtime through all connected
EtherCAT stations. The master measures this time. A reserve time can be
added (e.g., 10 % of the PLC cycle time) to allow for telegram jitter.
• The Master User Shift Time can be increased for further protection against
jittering.
• The Slave User Shift Time specifies the phase position of the SYNC0 signal
in relation to the sum of Master Shift Time and Master User Shift Time. This
value can be used to shift the phase position of the SYNC0 signal in the
positive and negative direction to counteract slave jitter. Note that you must
set this time separately for each slave.
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