Supermicro x10qbi - Memory RAS and Interleaving Settings

4-16
X10QBi Platform User’s Manual
• Memory Channel
• DIMM Frequency
Memory RAS (Reliability Availability Serviceability)
Conguration
This submenu will display the following items:
• Current Memory Mode
• Mirroring
• Sparing
Memory Rank Sparing
This item indicates if memory rank sparing is supported by the motherboard.
Memory rank sparing enhances system performance. The options are Disabled
and Enabled.
Spare Error/Memory Correctable Thr (Threshold)
Use this feature to set the correctable error threshold for spare memory modules.
The default setting is 10.
Leaky Bucket Low Bit
Use this feature to set the Low Bit value for the Leaky Bucket algorithm which
is used to check the data transmissions between CPU sockets and the memory
controller. The default setting is 40.
Leaky Bucket High Bit
Use this feature to set the High Bit value for the Leaky Bucket algorithm which
is used to check the data transmissions between CPU sockets and the memory
controller. The default setting is 41.
Memory Interleaving
Use this feature to set the DIMM memory interleaving mood. The options are NUMA
(1-way) Node Interleave; 2-way Node Interleave; 4-way Node Interleave; 8 Way
Interleaving, inter-socket; and Auto.
Channel Interleaving
Use this feature to set the DIMM channel interleaving mood. The options are Auto,
1-way Interleave, 2-way Interleave, 3-way Interleave, and 4-way Interleave.