TECO A510-2001-H - Page 243

4-189
20- 10
Speed Observer Integral(I) Time 1
Range
【0.01~10.00】Sec
20- 11
Speed Observer Propotional(P) Gain2
Range
【0.00~2.55】
20- 12
Speed Observer Integral(I) Time 2
Range
【0.01~10.00】Sec
20- 13
Low-pass filter Time constant of speed feedback 1
Range
【1~1000】mSec
20- 14
Low-pass filter Time constant of speed feedback 2
Range
【1~1000】mSec
20- 15
ASR gain change frequency 1
Range
【0.0~400.0】Hz
20- 16
ASR gain change frequency 2
Range
【0.0~400.0】Hz
20- 17
Torque compensation gain at low speed
Range
【0.00~2.50】
20- 18
Torque compensation gain at high speed
Range
【-10~10】%
. The following figure is the architecture of speed control cycle (ASR).
(a) V/F + PG control mode:
.Speed control system （ASR） tunes the output frequency, to make the frequency
reference and the feedback speed close to 0.
Figure 4.3.107 Speed control architecture (V/F + PG)
. When the multi-function input (03-00 to 03-07) is set to 42 (PG is invalid), the input can
be used to enable or disable the speed control loop system (ASR).
(b)SLV control mode :
.Speed control system (ASR) tunes the output frequency, to make the frequency
reference and the feedback speed close to 0.
. The ASR controller of SLV mode is designed with a speed estimate device to estimate
the motor speed. In order to reduce the interference in the speed feedback signal, a
low-pass filter and speed feedback compensator can be added.
. ASR integrator output can be removed or restricted. All outputs are through the
low-pass filter. The torque will also be limited.