ADDRESS LATCH.
Address Latches U364 and U562
hold the 16-bit address output by the Waveform /lP. The
latched address then remains on the address bus for the
rest of the Waveform ,uP cycle to access that memory
location for readsor writes.
WAVEFORM /lP ADDRESS ENABLING.
The 2.5 MHz
System Clock signal CLK1 from the Clock Divider U710
(diagram 7) is inverted by U866E and ORed with the
skewed 2.5 MHz CLK3 signal by OR-gate U264B.The tim-
ing of this ORed signal is such that the output of U264B
goes HI when the addresson the input pins of Waveform
Address Registers U562 and U364 is guaranteed to be
valid. Inverter U270B inverts the output from the OR-gate
(WVMA-waveform valid-memoryaddress),and when that
output again goes LO, the rising edge of the inverted
WVMA signal on the clock input of the WaveformAddress
Registers latches the 16-bit address from the Waveform
,uPinto the registers.
In AVG acquisition mode, data from the Acquisition
Memory is averagedwith the waveform datain the Save
Memory, and the Save Memory is then rewritten with the
averaged waveform data. Waveform adds, multiplies,
expansions, and interpolations are performed by the
Waveform,uPon the Save Memory data prior to transfer
to the DisplayMemory for display.
When in ENVELOPEacquisitionmode with more than a
one acquisition accumulation to be displayed, the data
bytes stored in Save Memory are not automatically
overwritten with each acquisition. As the data bytes are
being transferred from Acquisition Memory to Save
Memory, they are compared by the Waveform ,uP.
If
the
new data byte does not exceed the current maximum or
minimum value in Save Memory location that it is being
comparedwith, that Save Memory location is not overwrit-
ten (until the envelope acquisition is reset to start a new
accumulation).
WAVEFORM /lP OPERATION.
When the Waveform ,uP
gains control of the waveform bus, it sequentially moves
the 1024 data points for each channel(512 min/max pairs
in envelope)from the Acquisition Memory (diagram 8) to
the Save Memory (U350).When the Waveform,uPdoes a
display update, it selects the required data points needed
for each waveform display requested (according to the
mode selected)from Save Memoryand movesthem to the
Display Memory (diagram 16). At the end of the display
update, DISDN (display done) from the Display Control
(diagram 17) goes HI to interrupt the Waveform /lP (and
the SystemIlP if the Waveform ,uPis also done and per-
mits the signal to be gated to the System ,uPvia AND-gate
U580B, diagram 1). This tells the Waveform ,uPthat the
current display cycle has completed and the next update
to DisplayMemorymay be started.
3-22
The first instruction in the task list tells the Waveform
ILPwhat is to be done. The ILPthen switches to the rou-
tine in ROM to get the instructions that do that job. Part
of that routine might be to get the argumentsfor the task.
When the arguments are in place, the Waveform ILPthen
finishes the task routine. When done with the first task,
the WaveformILPlooks at the task list for the next task. It
keeps doing the commands and arguments for each task
until the entire task list is done. The last task of everytask
list is the WPDN task (Waveform Processor Done).Upon
receivingthat task, the Waveform ILPsets the WPDN bit
to the System ILPInterrupt circuit HI, informingthe System
ILPthat it is finished. It then enters a"loop forever" state
to wait for its next set of instructions. When the System
,uP checks the interrupt register and finds WPDN HI, it
resets the Waveform ILPand writes a new list of tasks to
the WaveformILPCommandRAM.
Upon release of WPRESET,the Waveform ,uPfetches
the first two 16-bitwords from its instruction ROMs, U480
and U490, at a 5 MHz rate and forms them into a 32-bit
instruction word. Waveform ILP U470 then executes the
first instruction and at the same time it"prefetches" the
next 32-bit word from the instruction ROM (the next
instruction). The Waveform ,uPcontinues fetching instruc-
tions to carry out its internal initializationroutine until that
is completed, and it then looks in Command RAM at a
vectoredlocationto find the first task in the task list.
Initially,with power-on,WPRESET(WaveformILPreset)
from Processor Controlled Register U860 (diagram 1) will
be LO, holding the processor reset via U270C. This reset
remains in effect until the System ,uPwrites a HI bit to the
WPRESEToutput of U860to removethe reset and enable
the Waveform ILP. The System ILP also holds the
WaveformILPreset while it is updatingthe commandlist in
RAM of the next task that the WaveformILPis to perform.
This reset occurs at the completion of each set of tasks
given to the Waveform ILPand is releasedwhen the new
task list is in place in the Waveform ILPCommand RAM,
U440.
Waveform J.LP
Waveform ILPU470 is a speciallydesigned,high-speed
microprocessorwith a 16-bitmultiplexeddata and address
bus and separate 12-bit instruction-address and 16-bit
instruction-data busses. The Waveform ILPis clocked at
2.5 MHz and executes one instruction each clock cycle.
Internally the WaveformILPuses a 32-bit wideinstruction
word. Therefore,to enable it to obtain a complete instruc-
tion for execution with each ILP cycle, instructions are
"double-prefetched." Two 16-bit halves of the instruction
are fetched from the instruction bus with each cycle at a
5 MHz rate, so that theinstructionwords are 32 bits wide.
Theory of Operation-2430 Service
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