3-23
Addresses residing in the System ILP memory space
should not access the Waveform ILP memory space, and
are thus excluded from access by U850 and the associ-
ated input logic gates. Addresses not excluded will cause
a System ILPaccess into the Waveform ILPmemory space.
b. It is a memory-mapped I/O location and address
bits A3 and A4 are HI (the address is within the top
eight I/O addresses of the System ILP).
a. HMMIO is LO- The address is not a System ILP
memory-mapped I/O location, or
3. Address bit AF is LO- This is not a "system ROM"
access; and either:
2. MAIN HI-This is not a "system RAM" access.
1. BUSGRANT LO-Waveform ILPhas relinquished the
busses.
The conditions that must be present for NOR-gate
U850 to produce an enable to the Bus Connect Data
Buffer are:
NOR-gate U850, performing a negative-logic NAND
function, is used to check for proper addressing to connect
the System ILP and Waveform ILP data busses together.
When all of the addressing conditions are met, Bus Con-
nect Data Buffer U552 is enabled by the output of U850
via inverter U254D, and the two busses are connected
together. The direction of the transfer through the buffer is
controlled by the WR (write) line from the System ILP,
depending on whether a write access (WR is LO) or a read
access (WR is HI) is being done.
From inverter U254B, BUSGRANT turns on Bus Con-
nect Address Buffers U262, U260, and U564 to connect
the System ILP address bus and control signal lines to
their counterparts from the Waveform ILP. Bus Connect
Data Buffer U552, a bidirectional device, is then enabled
and directed by control signals from the System ILP for
data transfers to and from the Waveform ILPdata bus.
When Waveform ILP U470 is being held reset (inactive)
and cannot possibly respond to a BUSREO, the System
ILPinstead asserts BUSTAKE to OR-gate U332D when it
needs to take control of the Waveform ILPaddress space.
The System ILPcan also assert BUSTAKE during diagnos-
tics in the event of a Waveform ILPfailure to release the
bus after a BUSREO is given.
Theory of Operation-2430 Service
SYSTEM ILPACCESS. When the System ILPneeds to
do an access in the Waveform ILP address space, it
checks its software copy of PCREG to see if the
Waveform ILP is reset. If it is not reset, the System ILP
asserts BUSREO (bus request) to the Waveform ILP and
waits until the Waveform ILP outputs a BUSACK (bus
acknowledge) to OR-gate U332D. The output of U332D is
the BUSGRANT signal that, when HI, disables the
Waveform ILPdata buffers, address registers, and memory
control lines.
To write data out of the Waveform ILPto the WD bus,
the WRD level applied to the direction-enabling pin of
U360 will be HI. The center eight bits of the Waveform ILP
data bus will then be buffered onto the WD (waveform
data) bus by U360 and written to the currently addressed
location. During writes to the WD bus, the HI level of WRD
disables buffer U560, via U250B and U250A, to isolate it
from the Waveform ILPaddress/data bus.
The four least significant bits (LSB) and the four most
significant bits (MSB) of the data applied to the WD bus
come from buffer U560, which is enabled via U250B and
U250A for processor reads. The four LSBs are always LO
(guard bits), while the four MSBs will be set to the same
level as the WD7 bit (sign-extended) of the center eight
bits. This placement of the 8-bit data in the center of the
16-bit bus provides a reasonable tradeoff between
dynamic range (12 bits) and guard bits (4 bits).
WAVEFORM ILP READ/WRITE ENABLING. Once
latched, the address is removed from the bus and,
depending on whether ILPU470 is supposed to be reading
or writing, data will be read into the processor from data
bus buffers U360 and U560 or written to the WD
(waveform data) bus via U360, a bidirectional data bus
buffer. To read data into the processor, the HI R/W (read-
write) signal is applied to NAND-gate U870C where it is
NANDed with CLK1. During the half period that CLK1 is HI
(CLK1 is LO), the gated output from U870C is the WRD
(waveform processor read) in its LO (asserted) state. The
LO is applied to the direction-enabling input of bidirectional
buffer U360 via U542B. This LO enables U360 for a read
from the WD (waveform data) bus, and the addressed 8-bit
word on the WD bus is applied to the center eight lines of
the processor 16-bit address/data bus.
Test point TP562 on address line WAA provides a
trigger source for an external test oscilloscope when exa-
mining address waveforms in the Waveform ILP "KER-
NEL" mode. As the KERNEL mode exercises address
lines WAO-WAA, WAA is used as the trigger point.
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