The 4K block of addresses from 5000h to 5FFFh, when
selected, is further decoded into two, 2K blocks by U250C,
U254E, and U250D. In this block of memory, address line
WAB is used to select either Command Memory U440 via
OR-gate U250C or Coefficient Memory U432 via OR-gate
U250D and inverter U254E. Bidirectional bus buffer U352
(RAM Buffer) is enabled via AND-gate U580D for data
transfers to or from either RAM for this entire address
block.
The next three outputs from U570, DISP, DATI, and
ACO, are used to select the Display and Display Attribute
Memories (diagram 16) and the Acquisition Memory
(diagram 8) respectively.
A LO output selection to either YO or Y1 of Decoder
U570 will cause AND-gate U580C (functioning as a
negative-logic OR gate) to output a LO SAVE enable to
"Save" RAM U350 via 0244 and 0332. The Save RAM
resides in the first 8K of address space, OOOOhto 1FFFh.
This storage space is where waveform data is placed for
saving while the oscilloscope is turned off. The chip-select
circuit between the SAVE output of U580C and the low-
power RAM chip U350 is identical to that for the System
,uP nonvolatile RAM (U664, diagram 1). The circuit pro-
vides for chip selection during normal operation and high-
impedance isolation of the Save RAM chip-select input
when power is off. The chip-select circuit is explained
more fully in the "Save Memory Keep-Alive" description.
Writing to or reading from any of the Waveform J.LPRAM
space is done via bidirectional bus buffer U352. When
Save RAM U350 is selected by the SAVE line going La,
U352 is also enabled via AND-gate U580D. The direction
of the data transfer is determined by the state of the
WWR (waveform write) control line.
Block decoding is done by one-of-eight decoder U570,
which uses address lines WAC-WAF to separate the
addresses below 32K into eight, 4K blocks. Decoder U570
is enabled when a valid address (WVMA HI) below 32K
(address bit WAF La) is placed on the memory address
bus by either the Waveform J.LPor the System ,uP. The
next three lower address lines (WAE, WAD, and WAC)
determine which one of the eight outputs of the Decoder
will be selected. Table 3-4 illustrates this address
decoding.
The Address Decode circuit monitors the Waveform J.LP
address bus to develop the appropriate enabling signals to
the memory or I/O device that is to be accessed.
Address Decode
3-24
Manually removing jumper P128 disables the Waveform
ROMs and places their outputs into the high-impedance
state. The pull-up and pull-down resistors within resistor
packs R474 and R590 place a "NOP" (no-operation)
instruction byte on the instruction bus. A NOP command
causes the Waveform J.LPto increment through the first 12
bits of its address range on the 16-bit DAD bus and
through all the addresses of its IA bus. This "KERNEL"
mode allows the Waveform J.LPaddress bus and address
decoding to be exercised for troubleshooting and diagnos-
tic purposes.
The addresses of instructions to be read are deter-
mined by the 12 instruction-address bits output from the
Waveform J.LPand by the state of the 5 MHz clock. The 12
address bits from U470 are the most significant address
bits for any given instruction. The 5 MHz clock applied to
ROM address inputs AO through delay line DL580 and
associated components provides the least significant
address bit with sufficient delay to provide the needed
data-hold time. The state of the 5 MHz clock will be LO to
access the first 16 bits of an instruction word. The state of
the AO address line then goes HI, and the second half of
the 32-bit instruction is obtained from the next higher
memory location. This manner of address selection is the
"double-fetch" of instruction data mentioned previously in
the Waveform J.LPdescription.
Waveform J.LPROMs, U480 and U490, are enabled by
three chip selects each. During normal operation, WFM
KERNEL jumper (P128) is installed, and the CS1 chip
selects of both ROMs are enabled. Chip select CS2 of
both ROMs are addressed by the Waveform J.LPIAA bit to
access the memory locations, and chip select CS3 of both
ROMs is permanently enabled by +5 V via W380. When
the ROMs are enabled by the IAA address line from the
Waveform J.LP,data from the addressed location is output
to the 16-bit instruction data bus of the Waveform J.LP.In
this implementation, jumper W378 is left out, but it can be
added for future expansion of the addressing by using the
lAB bit to control the CS3 line. In that case, jumper W380
would be removed from the circuit to disconnect the + 5 V
supply from the CS3 input pins.
The Waveform J.LPROM consists of two, 4K-x-8-bit
ROM devices connected in parallel to form a 4K-x-16-bit
storage memory for Waveform J.LPwaveform data handling
commands. The Waveform J.LP"double-fetches" data from
this ROM space by reading in two 16-bit bytes of com-
mand data during each Waveform J.LPclock cycle. This
method of reading the commands makes the Waveform J.LP
command memory space look like a 2K-x-32-bit ROM. The
32-bit instruction word formed by the two fetches ade-
quately defines any Waveform J.LPoperation and allows the
Waveform J.LPto execute one instruction for each 2.5 MHz
clock cycle.
Waveform
~p
ROM
Theory of Operation-2430 Service
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