Theory of Operat ion
Main Board
Serial Digital Input
Processing
The serial digital circuitry receives the SDI input streams after they have been
equalized, from e ither the Mezzanine board or the EYE/PHY board, depending
on the installed options. The SDI streams are deserialized and passed to the
DSP FPGA where they undergo measurement and raster processing. The signal
informatio
n is then passed to the DSY FPGA for picture processing, recursion,
and display combining. The result is shown on the LCD display, and also provided
to the external XGA connector. The signal is also reserialized and applied to a
multiplexer, which is used to select the processed signal or either equalized input
signal for routing back to the SDI Out rear panel connector.
Reference Input
The Reference input is a passive loopthrough, which is AC coupled and buffered.
Operation varies, depending on whether the instrument is operating in digital
or composite input mode. For digital inputs the reference signal is applied to a
sync separator whose output is supplied to the DSP FPGA, where the timing
inform
ation is derived. For composite inputs, the reference signal is routed to the
Option CPS composite input board, where a 10-bit ADC digitizes the signal. The
digitized signal is then routed back to the DSP FPGA on the main board so the
timing information can be derived, as with the digital process.
Digital Wav eform
Processing Engine
The parallel data streams from the Composite and SDI video inputs are applied to
the waveform processing FPGA. This block deformats, up-samples, interpolates,
demodulates, and otherwise processes the data to generate the signals needed
to create the displays.
Rasterizing Engine
The Rasterizer engine resides in the same DSP FPGA as the waveform processing
engine. This block builds up the variable intensity images in the fast static RAM.
For e ach pixel of the display, the Rasterizer Engine increments the intensity of that
pixel every time the waveform hits its coordinates. As a result the waveform areas
h
it more frequently are brighter. For any given frame, the intensity map is built up
in one memory chip and read out of the other. The functions swap on the next field.
Recursion a nd Picture
Processing Engine
The output of the rasterizer feeds the picture and recursive processing engine
in the second large FPGA. This engine adds the previous frame to the present
frame to reduce flicker and improve brightness. It also converts the picture and
waveform signals from the input rate of 50 or 59.94 Hz to 60 Hz frame rate to
work with the XGA monitor. The picture and w aveform data combine with the
graphics and audio bar information from the control processor, and then output
to the XGA DAC to drive the external monitor. Note that the parallel data from
the serial digital inputs connect d irec tly to this FPGA to provide the picture
functionality, bypassing the waveform processing engine.
WFM6120, WFM7020, and WFM7120 Waveform Monitors Service Manual 2–3
To Next Page
Loading...
Need help?
General
