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SPRS717H –OCTOBER 2011–REVISED MAY 2015
Table 7-79. Switching Characteristics for McASP
(1)
(see Figure 7-87)
OPP100 OPP50
NO. PARAMETER UNIT
MIN MAX MIN MAX
Cycle time, McASP[x]_AHCLKR and
9 t
c(AHCLKRX)
20
(2)
40 ns
McASP[x]_AHCLKX
Pulse duration, McASP[x]_AHCLKR and
10 t
w(AHCLKRX)
0.5P – 2.5
(3)
0.5P – 2.5
(3)
ns
McASP[x]_AHCLKX high or low
Cycle time, McASP[x]_ACLKR and
11 t
c(ACLKRX)
20 40 ns
McASP[x]_ACLKX
Pulse duration, McASP[x]_ACLKR and
12 t
w(ACLKRX)
0.5P – 2.5
(3)
0.5P – 2.5
(3)
ns
McASP[x]_ACLKX high or low
ACLKR and
Delay time, McASP[x]_ACLKR and
0 6 0 6
ACLKX int
McASP[x]_ACLKX transmit edge to
McASP[x]_AFSR and
ACLKR and
2 13.5 2 18
McASP[x]_AFSX output valid
ACLKX ext in
13 t
d(ACLKRX-AFSRX)
ns
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to ACLKR and
McASP[x]_AFSR and ACLKX ext 2 13.5 2 18
McASP[x]_AFSX output valid with out
Pad Loopback
Delay time, McASP[x]_ACLKX ACLKX int 0 6 0 6
transmit edge to McASP[x]_AXR
ACLKX ext in 2 13.5 2 18
output valid
14 t
d(ACLKX-AXR)
ns
Delay time, McASP[x]_ACLKX
ACLKX ext
transmit edge to McASP[x]_AXR 2 13.5 2 18
out
output valid with Pad Loopback
Disable time, McASP[x]_ACLKX ACLKX int 0 6 0 6
transmit edge to McASP[x]_AXR
ACLKX ext in 2 13.5 2 18
output high impedance
15 t
dis(ACLKX-AXR)
ns
Disable time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR ACLKX ext
2 13.5 2 18
output high impedance with pad out
loopback
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) 50 MHz
(3) P = AHCLKR and AHCLKX period.
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