RM46L852
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SPNS185 –SEPTEMBER 2012
Table 5-16. MIBADC1 Event Trigger Hookup (continued)
PINMMR30[16] =
RTI Compare 0 RTI Compare 0 PINMMR30[16] = 0 and
011 4 ePWM_A1
Interrupt Interrupt 1 PINMMR30[17] =
1
100 5 N2HET1[12] N2HET1[17] — N2HET1[17] —
PINMMR30[24] =
PINMMR30[24] = 0 and
101 6 N2HET1[14] N2HET1[19] N2HET2[1]
1 PINMMR30[25] =
1
PINMMR31[0] = 0
110 7 GIOB[0] N2HET1[11] PINMMR31[0] = 1 ePWM_A2 and
PINMMR31[1] = 1
PINMMR31[8] = 0
111 8 GIOB[1] N2HET2[13] PINMMR31[8] = 1 ePWM_AB and
PINMMR31[9] = 1
NOTE
If ADEVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC1
module trigger input is made from the output side of the input buffer. This way, a trigger
condition can be generated either by configuring the function as output onto the pad (via the
mux control), or by driving the function from an external trigger source as input. If the mux
control module is used to select different functionality instead of the ADEVT, N2HET1[x] or
GIOB[x] signals, then care must be taken to disable these signals from triggering
conversions; there is no multiplexing on the input connections.
If N2HET2[5], ePWM_B, N2HET1[17], N2HET1[19], N2HET2[1], N2HET1[11], ePWM_S2,
N2HET2[13] or ePWM_AB is used to trigger the ADC the connection to the ADC is made
directly from the N2HETx or ePWM module outputs. As a result, the ADC can be triggered
without having to enable the signal from being output on a device terminal.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
5.4.2.2 MIBADC2 Event Trigger Hookup
Table 5-17. MIBADC2 Event Trigger Hookup
Trigger Event Signal
Group Source
Select, G1SRC, PINMMR30[0] = 0 and PINMMR30[1] = 1
Event #
PINMMR30[0] = 1
G2SRC or
Control for Control for
(default)
Option A Option B
EVSRC
Option A Option B
000 1 AD2EVT AD1EVT — AD1EVT —
PINMMR31[16] =
PINMMR31[16] = 0 and
001 2 N2HET1[8] N2HET2[5] ePWM_B
1 PINMMR31[17] =
1
010 3 N2HET1[10] N2HET1[27] — N2HET1[27] —
PINMMR31[24] =
RTI Compare 0 RTI Compare 0 PINMMR31[24] = 0 and
011 4 ePWM_A1
Interrupt Interrupt 1 PINMMR31[25] =
1
100 5 N2HET1[12] N2HET1[17] — N2HET1[17] —
PINMMR32[0] = 0
101 6 N2HET1[14] N2HET1[19] PINMMR32[0] = 1 N2HET2[1] and
PINMMR32[1] = 1
Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 127
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