Texas Instruments RM46L852 - Page 153

PRODUCTPREVIEW
SPICLK
(clock polarity=0)
SPISIMO
SPICSn
Master Out Data Is Valid
9
SPICLK
(clock polarity=1)
SPIENAn
10
Write to buffer
11
8
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
3
2
1
54
66
7
RM46L852
www.ti.com SPNS185 –SEPTEMBER 2012
Figure 5-14. SPI Master Mode External Timing (CLOCK PHASE = 0)
Figure 5-15. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 153
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