RM46L852
www.ti.com
SPNS185 –SEPTEMBER 2012
The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
Copyright © 2012, Texas Instruments Incorporated System Information and Electrical Specifications 85
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